Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 33
PIC18F87K90 FAMILY
PORTJ is a bidirectional I/O port.
RJ0 62 I/O ST Digital I/O.
RJ1/SEG33
RJ1
SEG33
61
I/O
O
ST
Analog
Digital I/O.
SEG33 output for LCD.
RJ2/SEG34
RJ2
SEG34
60
I/O
O
ST
Analog
Digital I/O.
SEG34 output for LCD.
RJ3/SEG35
RJ3
SEG35
59
I/O
O
ST
Analog
Digital I/O.
SEG35 output for LCD.
RJ4/SEG39
RJ4
SEG39
39
I/O
O
ST
Analog
Digital I/O.
SEG39 output for LCD.
RJ5/SEG38
RJ5
SEG38
40
I/O
O
ST
Analog
Digital I/O
SEG38 output for LCD.
RJ6/SEG37
RJ6
SEG37
41
I/O
O
ST
Analog
Digital I/O.
SEG37 output for LCD.
RJ7/SEG36
RJ7
SEG36
42
I/O
O
ST
Analog
Digital I/O.
SEG36 output for LCD.
V
SS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.
V
DD 32, 48, 71 P — Positive supply for logic and I/O pins.
AVSS 26 P — Ground reference for analog modules.
AVDD 25 P — Positive supply for analog modules.
ENVREG 24 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
12
P—
Core logic power or external filter capacitor connection.
External filter capacitor connection (regulator
enabled/disabled).
TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C™ = I
2
C/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K90 and PIC18F85K90 devices.
4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.