Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 27
PIC18F87K90 FAMILY
PORTD is a bidirectional I/O port.
RD0/SEG0/CTPLS
RD0
SEG0
CTPLS
72
I/O
O
O
ST
Analog
ST
Digital I/O.
SEG0 output for LCD.
CTMU pulse generator output.
RD1/SEG1/T5CKI/T7G
RD1
SEG1
T5CKI
T7G
69
I/O
O
I
I
ST
Analog
ST
ST
Digital I/O.
SEG1 output for LCD.
Timer5 clock input.
Timer7 external clock gate input.
RD2/SEG2
RD2
SEG2
68
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
RD3/SEG3
RD3
SEG3
67
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
RD4/SEG4/SDO2
RD4
SEG4
SDO2
66
I/O
O
O
ST
Analog
—
Digital I/O.
SEG4 output for LCD.
SPI data out.
RD5/SEG5/SDI2/SDA2
RD5
SEG5
SDI2
SDA2
65
I/O
O
I
I/O
ST
Analog
ST
I
2
C
Digital I/O.
SEG5 output for LCD.
SPI data in.
I
2
C™ data in.
RD6/SEG6/SCK2/SCL2
RD6
SEG6
SCK2
SCL2
64
I/O
O
I/O
I/O
ST
Analog
ST
I
2
C
Digital I/O.
SEG6 output for LCD.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C™ mode.
RD7/SEG7/SS2
RD7
SEG7
SS2
63
I/O
O
I
ST
Analog
TTL
Digital I/O.
SEG7 output for LCD.
SPI slave select input.
TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C™ = I
2
C/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K90 and PIC18F85K90 devices.
4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.