Datasheet

PIC18F87K90 FAMILY
DS39957D-page 22 2009-2011 Microchip Technology Inc.
VSS 9, 25, 41, 56 P Ground reference for logic and I/O pins.
V
DD 26, 38, 57 P Positive supply for logic and I/O pins.
AVSS 20 P Ground reference for analog modules.
AVDD 19 P Positive supply for analog modules.
ENVREG 18 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
10
P—
Core logic power or external filter capacitor connection.
External filter capacitor connection (regulator
enabled/disabled).
TABLE 1-3: PIC18F6XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
QFN/TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C™ = I
2
C/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K90 and PIC18F85K90 devices.
TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
MCLR
/RG5
RG5
9
I
I
ST
ST
Master Clear (input) or programming voltage (input).
This pin is an active-low Reset to the device.
General purpose, input only pin.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
49
I
I
I/O
CMOS
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input.
External clock source input. Always associated
with pin function, OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
50
O
O
I/O
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In certain oscillator modes, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C™ = I
2
C/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K90 and PIC18F85K90 devices.
4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.