Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 191
PIC18F87K90 FAMILY
13.4 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes.
When the RD16 control bit (T1CON<1>) is set, the
address for TMR1H is mapped to a buffer register for
the high byte of Timer1. A read from TMR1L loads the
contents of the high byte of Timer1 into the Timer1 High
Byte Buffer register. This provides the user with the
ability to accurately read all 16 bits of Timer1 without
having to determine whether a read of the high byte,
followed by a read of the low byte, has become invalid
due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits at once to both the high and low bytes of Timer1.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler; the
prescaler is only cleared on writes to TMR1L.
13.5 SOSC Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins, SOSCI (input) and SOSCO (amplifier
output). It is enabled by setting one of five bits: any of the
four SOSCEN bits in the TxCON registers (TxCON<3>)
or the SOSCGO bit in the OSCCON2 register
(OSCCON2<3>). The oscillator is a low-power circuit,
rated for 32 kHz crystals. It will continue to run during all
power-managed modes. The circuit for a typical LP
oscillator is depicted in Figure 13-2. Table 13-2 provides
the capacitor selection for the SOSC oscillator.
The user must provide a software time delay to ensure
proper start-up of the SOSC oscillator.
FIGURE 13-2: EXTERNAL COMPONENTS
FOR THE SOSC
OSCILLATOR
TABLE 13-2: CAPACITOR SELECTION FOR
THE TIMER
OSCILLATOR
(2,3,4,5)
The SOSC crystal oscillator drive level is determined
based on the SOSCSEL<1:0> (CONFIG1L<4:3>)
Configuration bits. The High Drive Level mode,
SOSCSEL<1:0> = 11, is intended to drive a wide
variety of 32.768 kHz crystals with a variety of load
capacitance (CL) ratings.
The Low Drive Level mode is highly optimized for
extremely low-power consumption. It is not intended to
drive all types of 32.768 kHz crystals. In the Low Drive
Level mode, the crystal oscillator circuit may not work
correctly if excessively large discrete capacitors are
placed on the SOSCO and SOSCI pins. This mode is
designed to work only with discrete capacitances of
approximately 3 pF-10 pF on each pin.
Crystal manufacturers usually specify a CL (Capaci-
tance Load) rating for their crystals. This value is
related to, but not necessarily the same as, the values
that should be used for C1 and C2 in Figure 13-2.
For more details on selecting the optimum C1 and C2
for a given crystal, see the crystal manufacture’s
applications information. The optimum value depends,
in part, on the amount of parasitic capacitance in the
circuit, which is often unknown. For that reason, it is
highly recommended that thorough testing and
validation of the oscillator be performed after values
have been selected.
Note: See the Notes with Table 13-2 for additional
information about capacitor selection.
C1
C2
XTAL
SOSCI
SOSCO
32.768 kHz
12 pF
12 pF
PIC18F87K90
Oscillator
Type
Freq. C1 C2
LP 32 kHz 12 pF
(1)
12 pF
(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stabil-
ity of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design
guidance only. Values listed would be
typical of a CL = 10 pF rated crystal
when SOSCSEL<1:0> = 11.
5: Incorrect capacitance value may result in
a frequency not meeting the crystal
manufacturer’s tolerance specification.