Datasheet
2009-2011 Microchip Technology Inc. DS39957D-page 101
PIC18F87K90 FAMILY
FB0h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/
T3DONE
T3GVAL T3GSS1 T3GSS0 0000 0x00
FB1h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC
RD16 TMR3ON 0000 0000
FB2h TMR3L Timer3 Register Low Byte xxxx xxxx
FB3h TMR3H Timer3 Register High Byte xxxx xxxx
FB4h CMSTAT CMP3OUT CMP2OUT CMP1OUT
— — — — — 111- ----
FB5h CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 0000
FB6h PIE4 CCP10IE
(3)
CCP9IE
(3)
CCP8IE CCP7IE
(3)
CCP6IE CCP5IE CCP4IE CCP3IE 0000 0000
FB7h PIR4 CCP10IF
(3)
CCP9IF
(3)
CCP8IF CCP7IF
(3)
CCP6IF CCP5IF CCP4IF CCP3IF 0000 0000
FB8h IPR4 CCP10IP
(3)
CCP9IP
(3)
CCP8IP CCP7IP
(3)
CCP6IP CCP5IP CCP4IP CCP3IP 1111 1111
FB9h PIE5 TMR7GIE
(3)
TMR12IE
(3)
TMR10IE
(3)
TMR8IE TMR7IE
(3)
TMR6IE TMR5IE TMR4IE 0000 0000
FBAh PIR5 TMR7GIF
(3)
TMR12IF
(3)
TMR10IF
(3)
TMR8IF TMR7IF
(3)
TMR6IF TMR5IF TMR4IF 0000 0000
FBBh CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
FBCh CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx
FBDh CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx
FBEh ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000
FBFh ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000
FC0h ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0—00 0000
FC1h ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 0000 0000
FC2h ADCON0
— CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000
FC3h ADRESL A/D Result Register Low Byte xxxx xxxx
FC4h ADRESH A/D Result Register High Byte xxxx xxxx
FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000
FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
FC7h SSP1STAT SMP CKE D/A
PSR/WUA BF 0000 0000
FC8h SSP1ADD MSSP Address Register in I
2
C™ Slave Mode. SSP1 Baud Rate Reload Register in I
2
C Master Mode 0000 0000
FC9h SSP1BUF MSSP Receive Buffer/Transmit Register xxxx xxxx
FCAh T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 —000 0000
FCBh PR2 Timer2 Period Register 1111 1111
FCCh TMR2 Timer2 Register 0000 0000
FCDh T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC
RD16 TMR1ON 0000 0000
FCEh TMR1L Timer1 Register Low Byte xxxx xxxx
FCFh TMR1H Timer1 Register High Byte xxxx xxxx
FD0h RCON IPEN SBOREN CM
RI TO PD POR BOR 0111 11qq
FD1h WDTCON REGSLP
—ULPLVLSRETEN— ULPEN ULPSINK SWDTEN 0—x0 —000
FD2h IPR5 TMR7GIP
(3)
TMR12IP
(3)
TMR10I
(3)
PTMR8IP TMR7IP
(3)
TMR6IP TMR5IP TMR4IP 1111 1111
FD3h OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 0110 q000
FD4h SPBRGH1 USART1 Baud Rate Generator High Byte 0000 0000
FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA TOPS2 TOPS1 TOPS0 1111 1111
FD6h TMR0L Timer0 Register Low Byte xxxx xxxx
FD7h TMR0H Timer0 Register High Byte 0000 0000
FD8h STATUS
— — —NOVZDCC---x xxxx
FD9h FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx
FDAh FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx
FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
---- ----
FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre--incremented (not a physical register) ---- ----
FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ----
FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ----
TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented in 64-pin devices (PIC18F6XK90).
3: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).