Datasheet

PIC18F87J90 FAMILY
DS39933D-page 78  2010 Microchip Technology Inc.
SPBRG1 EUSART Baud Rate Generator Low Byte 0000 0000 61, 259
RCREG1 EUSART Receive Register
0000 0000 61, 267
TXREG1 EUSART Transmit Register
0000 0000 61, 265
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0010 61, 256
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0000 000x 61, 257
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0
0000 0000 61, 185
LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00
0000 0000 61, 186
LCDCON LCDEN SLPEN WERR
— CS1 CS0 LMUX1 LMUX0 000- 0000 61, 184
EECON2 EEPROM Control Register 2 (not a physical register)
---- ---- 61, 90
EECON1
— — WPROG FREE WRERR WREN WR — --00 x00- 61, 90
IPR3
— LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP -111 1111 62, 114
PIR3
— LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF -000 0000 62, 108
PIE3
— LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE -000 0000 62, 111
IPR2 OSCFIP CMIP
— — BCLIP LVDIP TMR3IP — 11-- 111- 62, 113
PIR2 OSCFIF CMIF
— —BCLIFLVDIFTMR3IF— 00-- 000- 62, 107
PIE2 OSCFIE CMIE
— — BCLIE LVDIE TMR3IE — 00-- 000- 62, 110
IPR1
— ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP -111 1-11 62, 112
PIR1
— ADIF RC1IF TX1IF SSPIF — TMR2IF TMR1IF -000 0-00 62, 106
PIE1
— ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE -000 0-00 62, 109
OSCTUNE INTSRC PLLEN
(4)
TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 37, 62
TRISJ
(2)
TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 62, 138
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 62, 136
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
0001 1111 62, 134
TRISF TRISF7TRISF6TRISF5TRISF4TRISF3TRISF2TRISF1
— 1111 111- 62, 132
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3
— TRISE1 TRISE0 1111 1-11 62, 129
TRISD TRISD7TRISD6TRISD5TRISD4TRISD3TRISD2TRISD1TRISD0
1111 1111 62, 127
TRISC TRISC7TRISC6TRISC5TRISC4TRISC3TRISC2TRISC1TRISC0
1111 1111 62, 125
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
1111 1111 62, 122
TRISA TRISA7
(5)
TRISA6
(5)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 62, 119
LATJ
(2)
LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 62, 138
LATH
(2)
LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 62, 136
LATG U2OD U1OD
— LATG4 LATG3 LATG2 LATG1 LATG0 00-x xxxx 62, 134
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1
— xxxx xxx- 62, 132
LATE LATE7 LATE6 LATE5 LATE4 LATE3
—LATE1LATE0 xxxx x-xx 62, 129
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
xxxx xxxx 62, 127
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
xxxx xxxx 62, 125
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
xxxx xxxx 62, 122
LATA LATA7
(5)
LATA6
(5)
LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx 62, 119
TABLE 6-3: PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘ 0 ’. Reset states shown are
for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 18.4.3.2 “Address
Masking”
for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘ 0 ’. See Section 3.4.3 “PLL
Frequency Multiplier”
for details.
5: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit =
0 ); otherwise, they are disabled and these bits read as ‘ 0 ’.