Datasheet

PIC18F87J72 FAMILY
DS39979A-page 68 Preliminary  2010 Microchip Technology Inc.
SPBRG1 EUSART Baud Rate Generator Low Byte 0000 0000 51, 243
RCREG1 EUSART Receive Register
0000 0000 51, 251
TXREG1 EUSART Transmit Register
0000 0000 51, 249
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0010 51, 240
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0000 000x 51, 241
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0
0000 0000 51, 169
LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00
0000 0000 51, 170
LCDCON LCDEN SLPEN WERR
— CS1 CS0 LMUX1 LMUX0 000- 0000 51, 168
EECON2 EEPROM Control Register 2 (not a physical register)
---- ---- 51, 78
EECON1
— — WPROG FREE WRERR WREN WR — --00 x00- 51, 78
IPR3
— LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP -111 1111 52, 102
PIR3
— LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF -000 0000 52, 96
PIE3
— LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE -000 0000 52, 99
IPR2 OSCFIP CMIP
— — BCLIP LVDIP TMR3IP — 11-- 111- 52, 101
PIR2 OSCFIF CMIF
— —BCLIFLVDIFTMR3IF— 00-- 000- 52, 95
PIE2 OSCFIE CMIE
— — BCLIE LVDIE TMR3IE — 00-- 000- 52, 98
IPR1
— ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP -111 1-11 52, 100
PIR1
— ADIF RC1IF TX1IF SSPIF — TMR2IF TMR1IF -000 0-00 52, 94
PIE1
— ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE -000 0-00 52, 97
OSCTUNE INTSRC PLLEN
(3)
TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 27, 52
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
0001 1111 52, 122
TRISF TRISF7TRISF6TRISF5TRISF4TRISF3TRISF2TRISF1
— 1111 111- 52, 120
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3
— TRISE1 TRISE0 1111 1-11 52, 117
TRISD TRISD7TRISD6TRISD5TRISD4TRISD3TRISD2TRISD1TRISD0
1111 1111 52, 115
TRISC TRISC7TRISC6TRISC5TRISC4TRISC3TRISC2TRISC1TRISC0
1111 1111 52, 113
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
1111 1111 52, 110
TRISA TRISA7
(4)
TRISA6
(4)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 52, 107
LATG U2OD U1OD
— LATG4 LATG3 LATG2 LATG1 LATG0 00-x xxxx 52, 122
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1
— xxxx xxx- 52, 120
LATE LATE7 LATE6 LATE5 LATE4 LATE3
—LATE1LATE0 xxxx x-xx 52, 117
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
xxxx xxxx 52, 115
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
xxxx xxxx 52, 113
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
xxxx xxxx 52, 110
LATA LATA7
(4)
LATA6
(4)
LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx 52, 107
PORTG RDPU REPU RJPU
(2)
RG4RG3RG2RG1RG0 000x xxxx 52, 122
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1
— xxxx xxx- 52, 120
PORTE RE7 RE6 RE5 RE4 RE3
—RE1RE0 xxxx x-xx 52, 117
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
xxxx xxxx 52, 115
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
xxxx xxxx 52, 113
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
xxxx xxxx 52, 110
PORTA RA7
(4)
RA6
(4)
RA5RA4RA3RA2RA1RA0 xx0x 0000 52, 107
TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 18.4.3.2 “Address
Masking”
for details.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘ 0 ’. See Section 3.4.3 “PLL
Frequency Multiplier”
for details.
4: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit =
0 ); otherwise, they are disabled and these bits read as ‘ 0 ’.