Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 67
PIC18F87J72 FAMILY
TMR0H Timer0 Register High Byte 0000 0000 50, 125
TMR0L Timer0 Register Low Byte
xxxx xxxx 50, 125
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
1111 1111 50, 123
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
0110 q000 26, 50
LCDREG
— CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0 -011 1100 50, 173
WDTCON REGSLP
— — — — — —SWDTEN 0--- ---0 50, 326
RCON IPEN
—CMRI TO PD POR BOR 0-11 11q0 44, 50
TMR1H Timer1 Register High Byte
xxxx xxxx 50, 131
TMR1L Timer1 Register Low Byte
xxxx xxxx 50, 131
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 50, 127
TMR2 Timer2 Register
0000 0000 50, 134
PR2 Timer2 Period Register
1111 1111 50, 134
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 133
SSPBUF MSSP Receive Buffer/Transmit Register
xxxx xxxx 50, 203,
238
SSPADD MSSP Address Register in I
2
C™ Slave mode. MSSP1 Baud Rate Reload Register in I
2
C Master mode. 0000 0000 50, 238
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 50, 196,
205
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 50, 197,
206
SSPCON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 207,
208
GCEN
ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN
ADRESH A/D Result Register High Byte
xxxx xxxx 51, 281
ADRESL A/D Result Register Low Byte
xxxx xxxx 51, 281
ADCON0 ADCAL
— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 51, 273
ADCON1 TRIGSEL
— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0-00 0000 51, 274
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 275
LCDDATA4
— — — — — — — S32C0 xxxx xxxx 51, 171
LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0
xxxx xxxx 51, 171
LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0
xxxx xxxx 51, 171
LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0
xxxx xxxx 51, 171
LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0
xxxx xxxx 51, 171
LCDSE4
— — — — — — —SE32 0000 0000 51, 171
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24
0000 0000 51, 171
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16
0000 0000 51, 171
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08
0000 0000 51, 171
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
0000 0000 51, 299
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
0000 0111 51, 293
TMR3H Timer3 Register High Byte
xxxx xxxx 51, 137
TMR3L Timer3 Register Low Byte
xxxx xxxx 51, 137
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 51, 135
TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 18.4.3.2 “Address
Masking”
for details.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘ 0 ’. See Section 3.4.3 “PLL
Frequency Multiplier”
for details.
4: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit =
0 ); otherwise, they are disabled and these bits read as ‘ 0 ’.