Datasheet

PIC18F87J72 FAMILY
DS39979A-page 66 Preliminary  2010 Microchip Technology Inc.
TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 57
TOSH Top-of-Stack High Byte (TOS<15:8>)
0000 0000 49, 57
TOSL Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 49, 57
STKPTR STKFUL STKUNF
— Return Stack Pointer uu-0 0000 49, 58
PCLATU
— —bit 21
(1)
Holding Register for PC<20:16> ---0 0000 49, 57
PCLATH Holding Register for PC<15:8>
0000 0000 49, 57
PCL PC Low Byte (PC<7:0>)
0000 0000 49, 57
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 80
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 49, 80
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 49, 80
TABLAT Program Memory Table Latch
0000 0000 49, 80
PRODH Product Register High Byte
xxxx xxxx 49, 87
PRODL Product Register Low Byte
xxxx xxxx 49, 87
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
0000 000x 49, 91
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 49, 92
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
1100 0000 49, 93
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 72
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 73
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 73
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 73
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 49, 73
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 49, 72
FSR0L Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 49, 72
WREG Working Register
xxxx xxxx 49
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 72
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 73
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 73
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 73
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 49, 73
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 50, 72
FSR1L Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 50, 72
BSR
— — — — Bank Select Register ---- 0000 50, 62
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 72
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 73
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 73
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 73
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 50, 73
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 50, 72
FSR2L Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 50, 72
STATUS
— — —NOVZDCC ---x xxxx 50, 70
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 18.4.3.2 “Address
Masking”
for details.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘ 0 ’. See Section 3.4.3 “PLL
Frequency Multiplier”
for details.
4: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit =
0 ); otherwise, they are disabled and these bits read as ‘ 0 ’.