Datasheet

PIC18F87J72 FAMILY
DS39979A-page 52 Preliminary  2010 Microchip Technology Inc.
IPR3 PIC18F8XJ72 -111 1111 -111 1111 -uuu 1111
PIR3 PIC18F8XJ72 -000 0000 -000 0000 -uuu 0000
(3)
PIE3 PIC18F8XJ72 -000 0000 -000 0000 -uuu 0000
IPR2 PIC18F8XJ72 11-- 111- 11-- 111- uu-- uuu-
PIR2 PIC18F8XJ72 00-- 000- 00-- 000- uu-- uuu-
(3)
PIE2 PIC18F8XJ72 00-- 000- 00-- 000- uu-- uuu-
IPR1 PIC18F8XJ72 -111 1-11 -111 1-11 -uuu u-uu
PIR1 PIC18F8XJ72 -000 0-00 -000 0-00 -uuu u-uu
(3)
PIE1 PIC18F8XJ72 -000 0-00 -000 0-00 -uuu u-uu
OSCTUNE PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu
TRISG PIC18F8XJ72 0001 1111 0001 1111 uuuu uuuu
TRISF PIC18F8XJ72 1111 111- 1111 111- uuuu uuu-
TRISE PIC18F8XJ72 1111 1-11 1111 1-11 uuuu u-uu
TRISD PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu
TRISB PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu
TRISA
(5)
PIC18F8XJ72 1111 1111
(5)
1111 1111
(5)
uuuu uuuu
(5)
LATG PIC18F8XJ72 00-x xxxx 00-u uuuu uu-u uuuu
LATF PIC18F8XJ72 xxxx xxx- uuuu uuu- uuuu uuu-
LATE PIC18F8XJ72 xxxx x-xx uuuu u-uu uuuu u-uu
LATD PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu
LATC PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu
LATB PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5)
PIC18F8XJ72 xxxx xxxx
(5)
uuuu uuuu
(5)
uuuu uuuu
(5)
PORTG PIC18F8XJ72 000x xxxx 000u uuuu 000u uuuu
PORTF PIC18F8XJ72 xxxx xxx- uuuu uuu- uuuu uuu-
PORTE PIC18F8XJ72 xxxx x-xx uuuu u-uu uuuu u-uu
PORTD PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA
(5)
PIC18F8XJ72 xx0x 0000
(5)
uu0u 0000
(5)
uuuu uuuu
(5)
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.