Datasheet

PIC18F87J72 FAMILY
DS39979A-page 468 Preliminary  2010 Microchip Technology Inc.
Baud Rate Generator (BRG)..................................... 243
Auto-Baud Rate Detect ..................................... 246
Baud Rate Error, Calculating ............................ 243
Baud Rates, Associated Registers ................... 243
Baud Rates, Asynchronous Modes................... 244
High Baud Rate Select (BRGH Bit)................... 243
Operation in Power-Managed Modes ............... 243
Sampling ...........................................................243
Synchronous Master Mode ....................................... 254
Associated Registers, Receive ......................... 256
Associated Registers, Transmit ........................ 255
Reception.......................................................... 256
Transmission..................................................... 254
Synchronous Slave Mode ......................................... 257
Associated Registers, Receive ......................... 258
Associated Registers, Transmit ........................ 257
Reception.......................................................... 258
Transmission..................................................... 257
Extended Instruction Set
ADDFSR ................................................................... 377
ADDULNK................................................................. 377
CALLW......................................................................378
MOVSF ..................................................................... 378
MOVSS ..................................................................... 379
PUSHL ......................................................................379
SUBFSR ................................................................... 380
SUBULNK ................................................................. 380
External Oscillator Modes
Clock Input (EC and ECPLL Modes) .......................... 30
HS ............................................................................... 29
F
Fail-Safe Clock Monitor............................................. 319, 329
Exiting Fail-Safe Operation ....................................... 330
Interrupts in Power-Managed Modes ........................ 330
POR or Wake-up From Sleep ................................... 330
WDT During Oscillator Failure ..................................329
Fast Register Stack............................................................. 59
Firmware Instructions........................................................333
Flash Configuration Words................................................ 319
Flash Program Memory.......................................................77
Associated Registers ..................................................86
Control Registers ........................................................ 78
EECON1 and EECON2 ...................................... 78
TABLAT (Table Latch) Register.......................... 80
TBLPTR (Table Pointer) Register.......................80
Erase Sequence ......................................................... 82
Erasing........................................................................82
Operation During Code-Protect .................................. 86
Reading....................................................................... 81
Table Pointer
Boundaries Based on Operation......................... 80
Table Pointer Boundaries ........................................... 80
Table Reads and Table Writes ...................................77
Write Sequence .......................................................... 83
Write Sequence (Word Programming) ........................ 85
Writing.........................................................................83
Unexpected Termination..................................... 86
Write Verify .........................................................86
FSCM. See Fail-Safe Clock Monitor.
G
GOTO................................................................................ 355
H
Hardware Multiplier............................................................. 87
8 x 8 Multiplication Algorithms .................................... 87
Operation.................................................................... 87
Performance Comparison (table)................................ 87
I
I/O Ports............................................................................ 105
Input Voltage Considerations.................................... 105
Open-Drain Outputs.................................................. 106
Output Pin Drive ....................................................... 105
Pin Capabilities......................................................... 105
Pull-up Configuration ................................................ 106
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2
C Mode (MSSP)............................................................. 204
Acknowledge Sequence Timing ............................... 232
Associated Registers ................................................ 238
Baud Rate Generator ............................................... 225
Bus Collision
During a Repeated Start Condition................... 236
During a Stop Condition ................................... 237
Clock Arbitration ....................................................... 226
Clock Stretching........................................................ 218
10-Bit Slave Receive Mode (SEN = 1) ............. 218
10-Bit Slave Transmit Mode ............................. 218
7-Bit Slave Receive Mode (SEN = 1) ............... 218
7-Bit Slave Transmit Mode ............................... 218
Clock Synchronization and the CKP Bit.................... 219
Effects of a Reset ..................................................... 233
General Call Address Support .................................. 222
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2
C Clock Rate w/BRG.............................................. 225
Master Mode............................................................. 223
Baud Rate Generator ....................................... 225
Operation.......................................................... 224
Reception ......................................................... 229
Repeated Start Condition Timing ..................... 228
Start Condition Timing ...................................... 227
Transmission .................................................... 229
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 233
Multi-Master Mode.................................................... 233
Operation.................................................................. 209
Read/Write
Bit Information (R/W Bit)................ 209, 211
Registers .................................................................. 204
Serial Clock (SCK/SCL)............................................ 211
Slave Mode............................................................... 209
Address Masking .............................................. 210
Addressing........................................................ 209
Reception ......................................................... 211
Transmission .................................................... 211
Sleep Operation........................................................ 233
Stop Condition Timing .............................................. 232
INCF ................................................................................. 355
INCFSZ............................................................................. 356
In-Circuit Debugger........................................................... 331
In-Circuit Serial Programming (ICSP)....................... 319, 331
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 381
Indexed Literal Offset Mode.............................................. 381
Indirect Addressing ............................................................. 72
INFSNZ............................................................................. 356
Initialization Conditions for all Registers ....................... 49–54
Instruction Cycle ................................................................. 60
Clocking Scheme........................................................ 60
Flow/Pipelining............................................................ 60