Datasheet
Table Of Contents
- Analog Features:
- LCD Driver and Keypad Interface Features:
- Flexible Oscillator Structure:
- Low-Power Features:
- Peripheral Highlights:
- Special Microcontroller Features:
- Target Applications:
- Pin Diagram
- Typical Application Circuit: Single-Phase Power Meter
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers
- 3.0 Oscillator Configurations
- 3.1 Oscillator Types
- 3.2 Control Registers
- 3.3 Clock Sources and Oscillator Switching
- 3.4 External Oscillator Modes
- 3.5 Internal Oscillator Block
- 3.6 Effects of Power-Managed Modes on the Various Clock Sources
- 3.7 Power-up Delays
- 4.0 Power-Managed Modes
- 5.0 Reset
- 6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Program Memory and the Extended Instruction Set
- 6.6 Data Memory and the Extended Instruction Set
- 7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
- 7.4 Erasing Flash Program Memory
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
- 8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
- EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
- EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
- TABLE 8-1: Performance Comparison for Various Multiply Operations
- EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
- EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
- EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
- EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
- 9.0 Interrupts
- 10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 I/O Port Pin Capabilities
- 10.2 PORTA, TRISA and LATA Registers
- 10.3 PORTB, TRISB and LATB Registers
- 10.4 PORTC, TRISC and LATC Registers
- 10.5 PORTD, TRISD and LATD Registers
- 10.6 PORTE, TRISE and LATE Registers
- 10.7 PORTF, LATF and TRISF Registers
- 10.8 PORTG, TRISG and LATG Registers
- 11.0 Timer0 Module
- 12.0 Timer1 Module
- 13.0 Timer2 Module
- 14.0 Timer3 Module
- 15.0 Real-Time Clock and Calendar (RTCC)
- FIGURE 15-1: RTCC Block Diagram
- 15.1 RTCC Module Registers
- RTCC Control Registers
- RTCC Value Registers
- Alarm Value Registers
- 15.1.1 RTCC Control Registers
- 15.1.2 RTCVALH and RTCVALL Register Mappings
- Register 15-6: Reserved Register
- Register 15-7: Year: Year Value Register(1)
- Register 15-8: MontH: Month Value Register(1)
- Register 15-9: Day: Day Value Register(1)
- Register 15-10: Weekday: Weekday Value Register(1)
- Register 15-11: Hour: Hour Value Register(1)
- Register 15-12: MINUTE: Minute Value Register
- Register 15-13: SECOND: Second Value Register
- 15.1.3 ALRMVALH and ALRMVALL Register Mappings
- Register 15-14: ALRMMNTH: Alarm Month Value Register(1)
- Register 15-15: ALRMDAY: Alarm Day Value Register(1)
- Register 15-16: ALRMWd: Alarm Weekday Value Register(1)
- Register 15-17: ALRMHr: Alarm Hours Value Register(1)
- Register 15-18: ALRMMIN: Alarm Minutes Value Register
- Register 15-19: ALRMSEC: Alarm Seconds Value Register
- 15.1.4 RTCEN Bit Write
- 15.2 Operation
- 15.3 Alarm
- 15.4 Sleep Mode
- 15.5 Reset
- 15.6 Register Maps
- 16.0 Capture/Compare/PWM (CCP) Modules
- 17.0 Liquid Crystal Display (LCD) Driver Module
- FIGURE 17-1: LCD Driver Module Block Diagram
- 17.1 LCD Registers
- 17.2 LCD Clock Source
- 17.3 LCD Bias Generation
- 17.4 LCD Multiplex Types
- 17.5 Segment Enables
- 17.6 Pixel Control
- 17.7 LCD Frame Frequency
- 17.8 LCD Waveform Generation
- FIGURE 17-6: Type-A/Type-B Waveforms in Static Drive
- FIGURE 17-7: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 17-8: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 17-9: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 17-10: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 17-11: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 17-12: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 17-13: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 17-14: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 17-15: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive
- FIGURE 17-16: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive
- 17.9 LCD Interrupts
- 17.10 Operation During Sleep
- 17.11 Configuring the LCD Module
- 18.0 Master Synchronous Serial Port (MSSP) Module
- 18.1 Master SSP (MSSP) Module Overview
- 18.2 Control Registers
- 18.3 SPI Mode
- FIGURE 18-1: MSSP Block Diagram (SPI Mode)
- 18.3.1 Registers
- 18.3.2 Operation
- 18.3.3 Enabling SPI I/O
- 18.3.4 Open-Drain Output Option
- 18.3.5 Typical Connection
- 18.3.6 Master Mode
- 18.3.7 Slave Mode
- 18.3.8 Slave Select Synchronization
- 18.3.9 Operation in Power-Managed Modes
- 18.3.10 Effects of a Reset
- 18.3.11 Bus Mode Compatibility
- 18.4 I2C Mode
- FIGURE 18-7: MSSP Block Diagram (I2C™ Mode)
- 18.4.1 Registers
- 18.4.2 Operation
- 18.4.3 Slave Mode
- EXAMPLE 18-2: Address Masking Examples
- FIGURE 18-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Addressing)
- FIGURE 18-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)
- FIGURE 18-10: I2C™ Slave Mode Timing (Transmission, 7-bit Addressing)
- FIGURE 18-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Addressing)
- FIGURE 18-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Addressing)
- FIGURE 18-13: I2C™ Slave Mode Timing (Transmission, 10-bit Addressing)
- 18.4.4 Clock Stretching
- 18.4.5 General Call Address Support
- 18.4.6 Master Mode
- 18.4.7 Baud Rate
- 18.4.8 I2C Master Mode Start Condition Timing
- 18.4.9 I2C Master Mode Repeated Start Condition Timing
- 18.4.10 I2C Master Mode Transmission
- 18.4.11 I2C Master Mode Reception
- 18.4.12 Acknowledge Sequence Timing
- 18.4.13 Stop Condition Timing
- 18.4.14 Sleep Operation
- 18.4.15 Effects of a Reset
- 18.4.16 Multi-Master Mode
- 18.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
- FIGURE 18-27: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 18-28: Bus Collision During Start Condition (SDA Only)
- FIGURE 18-29: Bus Collision During Start Condition (SCL = 0)
- FIGURE 18-30: BRG Reset Due to SDA Arbitration During Start Condition
- FIGURE 18-31: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 18-32: Bus Collision During Repeated Start Condition (Case 2)
- FIGURE 18-33: Bus Collision During a Stop Condition (Case 1)
- FIGURE 18-34: Bus Collision During a Stop Condition (Case 2)
- TABLE 18-4: Registers Associated with I2C™ Operation
- 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 19.1 Control Registers
- 19.2 EUSART Baud Rate Generator (BRG)
- 19.3 EUSART Asynchronous Mode
- 19.4 EUSART Synchronous Master Mode
- 19.5 EUSART Synchronous Slave Mode
- 20.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)
- 20.1 Control Registers
- 20.2 AUSART Baud Rate Generator (BRG)
- 20.3 AUSART Asynchronous Mode
- 20.4 AUSART Synchronous Master Mode
- 20.5 AUSART Synchronous Slave Mode
- 21.0 12-Bit Analog-to-Digital Converter (A/D) Module
- Register 21-1: ADCON0: A/D Control Register 0
- Register 21-2: ADCON1: A/D Control Register 1
- Register 21-3: ADCON2: A/D Control Register 2
- FIGURE 21-1: A/D Block Diagram(1,2)
- FIGURE 21-2: Analog Input Model
- 21.1 A/D Acquisition Requirements
- 21.2 Selecting and Configuring Automatic Acquisition Time
- 21.3 Selecting the A/D Conversion Clock
- 21.4 Configuring Analog Port Pins
- 21.5 A/D Conversions
- 21.6 Use of the CCP2 Trigger
- 21.7 A/D Converter Calibration
- 21.8 Operation in Power-Managed Modes
- 22.0 Dual-Channel, 24-Bit Analog Front End (AFE)
- 23.0 Comparator Module
- Register 23-1: CMCON: Comparator Module Control Register
- 23.1 Comparator Configuration
- 23.2 Comparator Operation
- 23.3 Comparator Reference
- 23.4 Comparator Response Time
- 23.5 Comparator Outputs
- 23.6 Comparator Interrupts
- 23.7 Comparator Operation During Sleep
- 23.8 Effects of a Reset
- 23.9 Analog Input Connection Considerations
- 24.0 Comparator Voltage Reference Module
- 25.0 Charge Time Measurement Unit (CTMU)
- FIGURE 25-1: CTMU Block Diagram
- 25.1 CTMU Operation
- 25.2 CTMU Module Initialization
- 25.3 Calibrating the CTMU Module
- 25.4 Measuring Capacitance with the CTMU
- 25.5 Measuring Time with the CTMU Module
- 25.6 Creating a Delay with the CTMU Module
- 25.7 Operation During Sleep/Idle Modes
- 25.8 Effects of a Reset on CTMU
- 25.9 Registers
- 26.0 Special Features of the CPU
- 26.1 Configuration Bits
- 26.1.1 Considerations for Configuring PIC18F87J72 Family Devices
- TABLE 26-1: Mapping of the Flash Configuration Words to the Configuration Registers
- TABLE 26-2: Configuration Bits and Device IDs
- Register 26-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)
- Register 26-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
- Register 26-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
- Register 26-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
- Register 26-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)
- Register 26-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
- Register 26-7: DEVID1: Device ID Register 1
- Register 26-8: DEVID2: Device ID Register 2
- 26.1.1 Considerations for Configuring PIC18F87J72 Family Devices
- 26.2 Watchdog Timer (WDT)
- 26.3 On-Chip Voltage Regulator
- 26.4 Two-Speed Start-up
- 26.5 Fail-Safe Clock Monitor
- 26.6 Program Verification and Code Protection
- 26.7 In-Circuit Serial Programming
- 26.8 In-Circuit Debugger
- 26.1 Configuration Bits
- 27.0 Instruction Set Summary
- 27.1 Standard Instruction Set
- 27.2 Extended Instruction Set
- 28.0 Development Support
- 28.1 MPLAB Integrated Development Environment Software
- 28.2 MPLAB C Compilers for Various Device Families
- 28.3 HI-TECH C for Various Device Families
- 28.4 MPASM Assembler
- 28.5 MPLINK Object Linker/ MPLIB Object Librarian
- 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 28.7 MPLAB SIM Software Simulator
- 28.8 MPLAB REAL ICE In-Circuit Emulator System
- 28.9 MPLAB ICD 3 In-Circuit Debugger System
- 28.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 28.12 MPLAB PM3 Device Programmer
- 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 29.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 29.1 DC Characteristics: Supply Voltage PIC18F87J72 Family (Industrial)
- 29.2 DC Characteristics: Power-Down and Supply Current PIC18F87J72 Family (Industrial)
- 29.3 DC Characteristics: PIC18F87J72 Family (Industrial)
- 29.4 DC Characteristics: CTMU Current Source Specifications
- 29.5 AC (Timing) Characteristics
- 29.5.1 Timing Parameter Symbology
- 29.5.2 Timing Conditions
- 29.5.3 Timing Diagrams and Specifications
- FIGURE 29-4: External Clock Timing
- TABLE 29-7: External Clock Timing Requirements
- TABLE 29-8: PLL Clock Timing Specifications (Vdd = 2.15V to 3.6V)
- TABLE 29-9: Internal RC Accuracy (INTOSC and INTRC Sources)
- FIGURE 29-5: CLKO and I/O Timing
- TABLE 29-10: CLKO and I/O Timing Requirements
- FIGURE 29-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- TABLE 29-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements
- FIGURE 29-7: Timer0 and Timer1 External Clock Timings
- TABLE 29-12: Timer0 and Timer1 External Clock Requirements
- FIGURE 29-8: Capture/Compare/PWM Timings (CCP1, CCP2 Modules)
- TABLE 29-13: Capture/Compare/PWM Requirements (CCP1, CCP2 Modules)
- FIGURE 29-9: Example SPI Master Mode Timing (CKE = 0)
- TABLE 29-14: Example SPI Mode Requirements (Master Mode, Cke = 0)
- FIGURE 29-10: Example SPI Master Mode Timing (CKE = 1)
- TABLE 29-15: Example SPI Mode Requirements (Master Mode, CKE = 1)
- FIGURE 29-11: Example SPI Slave Mode Timing (CKE = 0)
- TABLE 29-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)
- FIGURE 29-12: Example SPI Slave Mode Timing (CKE = 1)
- TABLE 29-17: Example SPI Slave Mode Requirements (CKE = 1)
- FIGURE 29-13: I2C™ Bus Start/Stop Bits Timing
- TABLE 29-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)
- FIGURE 29-14: I2C™ Bus Data Timing
- TABLE 29-19: I2C™ Bus Data Requirements (Slave Mode)
- FIGURE 29-15: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms
- TABLE 29-20: MSSP I2C™ Bus Start/Stop Bits Requirements
- FIGURE 29-16: MSSP I2C™ Bus Data Timing
- TABLE 29-21: MSSP I2C™ Bus Data Requirements
- FIGURE 29-17: EUSART/AUSART Synchronous Transmission (Master/Slave) Timing
- TABLE 29-22: EUSART/AUSART Synchronous Transmission Requirements
- FIGURE 29-18: EUSART/AUSART Synchronous Receive (Master/Slave) Timing
- TABLE 29-23: EUSART/AUSART Synchronous Receive Requirements
- TABLE 29-24: A/D Converter Characteristics: PIC18F87J72 Family (Industrial)
- FIGURE 29-19: A/D Conversion Timing
- TABLE 29-25: A/D Conversion Requirements
- TABLE 29-26: Dual-Channel AFE Electrical Characteristics
- TABLE 29-27: Dual-Channel AFE Serial Peripheral Interface Specifications
- FIGURE 29-20: Serial Output Timing Diagram
- FIGURE 29-21: Serial Input Timing Diagram
- FIGURE 29-22: Data Ready Pulse Timing Diagram
- FIGURE 29-23: Specific Timing Diagrams
- 30.0 Packaging Information
- Appendix A: Revision History
- Appendix B: Dual-Channel, 24-Bit AFE Reference
- TABLE B-1: OVERSAMPLING RATIO SETTINGS
- TABLE B-2: Device data rates in function of mclk, osr AND PRESCALE
- TABLE B-3: OVERSAMPLING RATIO SETTINGS
- Step 1
- Step 2
- TABLE B-4: PGA Configuration Setting
- TABLE B-5: adc RESOLUTION vs. osr
- TABLE B-6: OSR = 256 output code examples
- TABLE B-7: OSR = 128 output code examples
- TABLE B-8: OSR = 64 output code examples
- TABLE B-9: OSR = 32 output code examples
- TABLE B-10: Phase Values With MCLK = 4 MHz, OSR = 256
- TABLE B-11: Register Groups
- TABLE B-12: Register Types
- TABLE B-13: Register map
- TABLE B-14: Register Map Grouping for Continuous read modes
- TABLE B-15: Phase Encoding Resolution By Oversampling Ratio
- INDEX
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2010 Microchip Technology Inc. Preliminary DS39979A-page 465
PIC18F87J72 FAMILY
INDEX
A
A/D
A/D Converter Interrupt, Configuring ........................ 277
Acquisition Requirements ......................................... 278
ADCAL Bit................................................................. 281
ADCON0 Register..................................................... 273
ADCON1 Register..................................................... 273
ADCON2 Register..................................................... 273
ADRESH Register............................................. 273, 276
ADRESL Register ..................................................... 273
Analog Port Pins, Configuring................................... 279
Associated Registers ................................................ 281
Configuring the Module............................................. 277
Conversion Clock (T
AD) ............................................ 279
Conversion Status (GO/DONE
Bit)........................... 276
Conversions.............................................................. 280
Converter Calibration................................................ 281
Converter Characteristics ......................................... 421
Operation in Power-Managed Modes ....................... 281
Overview ................................................................... 273
Selecting and Configuring Automatic
Acquisition Time ............................................... 279
Special Event Trigger (CCP)..................................... 280
Use of the CCP2 Trigger........................................... 280
Absolute Maximum Ratings .............................................. 389
AC (Timing) Characteristics .............................................. 404
Load Conditions for Device Timing
Specifications.................................................... 405
Parameter Symbology .............................................. 404
Temperature and Voltage Specifications .................. 405
Timing Conditions ..................................................... 405
ACKSTAT ......................................................................... 229
ACKSTAT Status Flag ...................................................... 229
ADCAL Bit......................................................................... 281
ADCON0 Register............................................................. 273
GO/DONE
Bit............................................................ 276
ADCON1 Register............................................................. 273
ADCON2 Register............................................................. 273
ADDFSR ........................................................................... 377
ADDLW ............................................................................. 340
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART). See AUSART.
ADDULNK......................................................................... 377
ADDWF............................................................................. 340
ADDWFC .......................................................................... 341
ADRESH Register............................................................. 273
ADRESL Register ..................................................... 273, 276
AFE
Analog Inputs ............................................................ 284
Block Diagram........................................................... 435
Boost Mode............................................................... 444
Data Ready Pin (DR
) ................................................ 454
Delta-Sigma ADC Architecture ................................. 284
Block Diagram .................................................. 444
Delta-Sigma Modulator ............................................. 444
Electrical Characteristics................................... 423–425
External Voltage Reference ...................................... 447
Internal Clock Chain.................................................. 449
Internal Registers...................................................... 456
Internal Voltage Reference ............................... 284, 447
Output Coding........................................................... 445
Output Data Rates (table) ......................................... 439
Phase Delay Block............................................ 284, 448
Power-On Reset ....................................................... 447
Programmable Gain Amplifiers................................. 284
Register Map .................................................... 285, 456
Registers
CONFIG1.......................................................... 462
CONFIG2.......................................................... 463
DATA_CHn....................................................... 457
GAIN................................................................. 459
PHASE ............................................................. 458
STATUS/COM.................................................. 461
Required Connections .............................................. 287
Resolution................................................................. 446
Serial Interface ................................................. 286, 449
Continuous Communication ............................. 452
Serial Interface Characteristics................................. 426
SINC
3
Filter ...................................................... 284, 444
Terminology...................................................... 438–443
Using ........................................................................ 288
Voltage Reference.................................................... 447
Analog-to-Digital Converter. See A/D.
ANDLW............................................................................. 341
ANDWF............................................................................. 342
Assembler
MPASM Assembler .................................................. 386
AUSART
Asynchronous Mode................................................. 264
Associated Registers, Receive......................... 267
Associated Registers, Transmit........................ 265
Receiver ........................................................... 266
Setting up 9-Bit Mode with
Address Detect......................................... 266
Transmitter ....................................................... 264
Baud Rate Generator (BRG) .................................... 262
Associated Registers........................................ 262
Baud Rate Error, Calculating............................ 262
Baud Rates, Asynchronous Modes .................. 263
High Baud Rate Select (BRGH Bit) .................. 262
Operation in Power-Managed Modes............... 262
Sampling .......................................................... 262
Synchronous Master Mode....................................... 268
Associated Registers, Receive......................... 270
Associated Registers, Transmit........................ 269
Reception ......................................................... 270
Transmission .................................................... 268
Synchronous Slave Mode......................................... 271
Associated Registers, Receive......................... 272
Associated Registers, Transmit........................ 271
Reception ......................................................... 272
Transmission .................................................... 271
B
Baud Rate Generator ....................................................... 225
BC..................................................................................... 342
BCF .................................................................................. 343
BF ..................................................................................... 229
BF Status Flag.................................................................. 229
Bias Generation (LCD)
Charge Pump Design Considerations ...................... 177
Block Diagrams
A/D............................................................................ 276
AFE, Required Connections ..................................... 287
Analog Input Model................................................... 277
AUSART Receive ..................................................... 266
AUSART Transmit .................................................... 264