Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 463
PIC18F87J72 FAMILY
REGISTER B-6: CONFIG2: CONFIGURATION REGISTER 2 (ADDRESS 0x0B)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 r-0
RESET_CH1 RESET_CH0 SHUTDOWN
<1>
SHUTDOWN
<0>
DITHER<1> DITHER<0> VREFEXT r
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 RESET<1:0>: Reset Mode Setting for ADCs bits
11 = Both CH0 and CH1 ADC are in Reset mode
10 = CH1 ADC in Reset mode
01 = CH0 ADC in Reset mode
00 = Neither Channel in Reset mode (default)
bit 5-4 SHUTDOWN<1:0>: Shutdown Mode Setting for ADCs bits
11 = Both CH0 and CH1 ADC are in Shutdown
10 = CH1 ADC is in Shutdown
01 = CH0 ADC is in Shutdown
00 = Neither Channel in Shutdown(default)
bit 3-2 DITHER<1:0>: Control for Dithering Circuit bits
11 = Both CH0 and CH1 ADC have dithering circuit applied (default)
10 = Only CH1 ADC has dithering circuit applied
01 = Only CH0 ADC has dithering circuit applied
00 = Neither channel has dithering circuit applied
bit 1 VREFEXT: Internal Voltage Reference Shutdown Control bit
1 = Internal Voltage reference disabled; an external voltage reference must be placed between
REFIN+/OUT and REFIN-
0 = Internal voltage reference enabled (default)
bit 0 Reserved: Resets as ‘0’; program as ‘1’ after any Reset event