Datasheet

PIC18F87J72 FAMILY
DS39979A-page 462 Preliminary  2010 Microchip Technology Inc.
B.6.5 CONFIGURATION REGISTERS
The Configuration registers contain settings for the
internal clock prescaler, the oversampling ratio, the
Channel 0 and Channel 1 width settings, the state of
the channel Resets and shutdowns, the dithering algo-
rithm control (for Idle tones suppression), and the
control bits for the external V
REF and external CLK.
REGISTER B-5: CONFIG1: CONFIGURATION REGISTER 1: (ADDRESS 0x0A)
R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 r-0 r-0
PRESCALE
<1>
PRESCALE
<0>
OSR<1> OSR<0> WIDTH<1> WIDTH<0> r r
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 PRESCALE<1:0>: Internal Master Clock (AMCLK) Prescaler Value bits
11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
bit 5-4 OSR<1:0>: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, DMCLK/DRCLK)
11 = 256
10 = 128
01 = 64 (default)
00 = 32
bit 3-2 WIDTH<1:0>: ADC Channel Output Data Word Width bits
11 = 24-bit mode on both channels
10 = 24-bit mode on Channel 1, 16-bit mode on Channel 0
01 = 16-bit mode on Channel 1, 24-bit mode on Channel 0
00 = 16 bit mode on both channels (default)
bit 1-0 Reserved: Maintain as ‘0’