Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 461
PIC18F87J72 FAMILY
REGISTER B-4: STATUS AND COMMUNICATION REGISTER (ADDRESS 0x09)
R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R-1 R-1
READ<1> READ<0> DR_LTY DR_HIZN DRMODE<1> DRMODE<0> DRSTATUS
<1>
DRSTATUS
<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 READ: Address Loop Setting bits
11= Address counter loops on entire register map
10= Address counter loops on register TYPES (default)
01= Address counter loops on register GROUPS
00= Address not incremented, continually read same single register
bit 5 DR_LTY: Data Ready Latency Control bit
1 = “No Latency” conversion, DR
pulses after 3 DRCLK periods (default)
0 = Unsettled data is available after every DRCLK period
bit 4 DR_HIZn: Data Ready Pin Inactive State Control bit
1 = The Data Ready pin default state is a logic high when data is NOT ready
0 = The Data Ready pin default state is high impedance when data is NOT ready (default)
bit 3-2 DRMODE<1:0>: Data Ready Pin (DR) Control bits
11= Both data ready pulses from ADC0 and ADC Channel 1 are output on the DR
pin
10= Data ready pulses from ADC Channel 1 are output on the DR
pin; DR from ADC Channel 0 are
not present on the pin
01= Data ready pulses from ADC Channel 0 are output on the DR
pin; DR from ADC Channel 1 are
not present on the pin
00= Data ready pulses from the lagging ADC between the two are output on the DR pin; the lagging
ADC selection depends on the PHASE register and on the OSR (default)
bit 1-0 DRSTATUS<1:0>: Data Ready Status bits
11= ADC Channel 1 and Channel 0 data not ready (default)
10= ADC Channel 1 data not ready, ADC Channel 0 data ready
01= ADC Channel 0 data not ready, ADC Channel 1 data ready
00= ADC Channel 1 and Channel 0 data ready