Datasheet

PIC18F87J72 FAMILY
DS39979A-page 458 Preliminary  2010 Microchip Technology Inc.
B.6.2 PHASE REGISTER
The PHASE register (PHASE<7:0>) is a 7 bits + sign,
MSB first, two’s complement register that indicates how
much phase delay there should be between Channel 0
and Channel 1.
The reference channel for the delay is Channel 1
(typically, the voltage channel when used in energy
metering applications) i.e., when PHASE register code
is positive, Channel 0 is lagging Channel 1.
When PHASE register code is negative, Channel 0 is
leading versus Channel 1.
The delay is give by the following formula:
EQUATION B-17:
B.6.2.1 Phase Resolution from OSR
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration (MCLK = 4 MHz). The
PHASE register coding depends on the OSR setting,
as shown in Table B-15.
Delay
Phase Register Code
DMCLK
--------------------------------------------------=
TABLE B-15: PHASE ENCODING
RESOLUTION BY
OVERSAMPLING RATIO
Oversampling
Ratio
Encoding
OSR
<1:0>
Value
#
Significant
Digits
Sign
Bit
Range
00 32 7 <6:0> <7> -128 to
+127
01 64 6 <5:0> <6> -64 to +63
10 128 5 <4:0> <5> -32 to +31
11 256 4 <3:0> <4> -16 to +15
REGISTER B-2: PHASE: PHASE REGISTER (ADDRESS 0x07)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PHASE<7> PHASE<6> PHASE<5> PHASE<4> PHASE<3> PHASE<2> PHASE<1> PHASE<0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PHASE<7-0>: CH0 Relative to CH1 Phase Delay bits
Delay = PHASE register two’s complement code/DMCLK (Default PHASE = 0)