Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 449
PIC18F87J72 FAMILY
B.4.10 INTERNAL AFE CLOCK
The AFE uses an external clock signal to operate its
internal digital logic. An internal clock generation chain
(Figure B-5) is used to produce a range of DRCLK
sampling frequencies.
For keeping specified ADC accuracy, AMCLK should
be kept between 1 and 5 MHz with BOOST off, or 1 and
8.192 MHz with BOOST on. Larger MCLK frequencies
can be used provided the prescaler clock settings allow
the AMCLK to respect these ranges.
FIGURE B-5: AFE INTERNAL CLOCK DETAIL
B.5 Serial Interface Description
B.5.1 OVERVIEW
The AFE is accessed for control and data output exclu-
sively through its dedicated Serial Peripheral Interface
(SPI). The interface is compatible with SPI Modes 0,0
and 1,1. Data is clocked out of the AFE on the falling
edge of SCK, and data is clocked in on the rising edge
of SCK. In these modes, SCK can Idle either high or
low.
Each SPI communication starts with a CS
falling edge
and stops with the CS
rising edge. Each SPI
communication is independent. When CS
is high, SDO
is in high-impedance, transitions on SCK and SDI have
no effect. Additional controls pins (ARESET
and DR)
are also provided on separate pins for advanced
communication.
The AFE’s SPI interface has a simple command
structure. The first byte transmitted is always the
control byte and is followed by data bytes that are 8-bit
wide. Both ADCs are continuously converting data by
default and can be reset or shut down through a
CONFIG2 register setting.
Since each ADC data is either 16 or 24 bits (depending
on the WIDTH bits), the internal registers can be
grouped together with various configurations (through
the READ bits) in order to allow easy data retrieval
within only one communication. For device reads, the
internal address counter can be automatically
incremented in order to loop through groups of data
within the register map. SDOA will then output the data
located at the ADDRESS (A<4:0>) defined in the con-
trol byte and then ADDRESS + 1 depending on the
READ<1:0> bits, which select the groups of registers.
These groups are defined in Section B.6.1 “ADC
Channel Data Output Registers” (Register Map).
The Data Ready pin (DR
) can be used as an interrupt for
a microcontroller and outputs pulses when new ADC
channel data is available. The ARESET pin acts like a
Hard Reset and can reset the AFE to its default power-up
configuration, independent of the microcontroller.
B.5.2 CONTROL BYTE
The control byte of the AFE contains two device
address bits (A<6:5>), 5 register address bits (A<4:0>)
and a read/write bit (R/W). The first byte transmitted to
the AFE is always the control byte.
The AFE interface is device-addressable (through
A<6:5>) so that multiple devices can be present on the
same SPI bus with no data bus contention. This
functionality enables three-phase power metering
systems containing an AFE and two other external
AFE-type chips, controlled by a single SPI bus (single
CS
, SCK, SDI and SDO pins). The default device
address bits are ‘00’.
FIGURE B-6: CONTROL BYTE
A read on undefined addresses will give an all zeros
output on the first and all subsequent transmitted bytes.
A write on an undefined address will have no effect and
will not increment the address counter either.
The register map is defined in Section B.6.1 “ADC
Channel Data Output Registers”.
PRESCALE<1:0>
1/
MCLK
AMCLK
1/4
DMCLK
1/OSR
DRCLK
OSR<1:0>
Clock Divider Clock Divider Clock Divider
CLKIA
Prescale
f
S
ADC
Sampling
Rate
f
D
ADC
Output
Data Rate
Digital Buffer
A6
A5
A4 A3
A2
A1
A0
R/W
Read
Write Bit
Register
Device
Address Bits
Address
Bits