Datasheet

PIC18F87J72 FAMILY
DS39979A-page 448 Preliminary  2010 Microchip Technology Inc.
B.4.8 ARESET EFFECT ON DELTA-SIGMA
MODULATOR/SINC FILTER
When the ARESET pin is low, both ADCs will be in
Reset and output code, 0x0000h. The RESET
pin per-
forms a Hard Reset (DC biases still on, part ready to
convert) and clears all charges contained in the
Sigma-Delta modulators. The comparator output is
‘0011’ for each ADC.
The sinc filters are all reset, as well as their double
output buffers. This pin is independent of the serial
interface. It brings the CONFIG registers to the default
state. When RESET
is low, any write with the SPI
interface will be disabled and will have no effect. The
output pins (SDOA, DR) are high impedance and no
clock is propagated through the chip.
B.4.9 PHASE DELAY BLOCK
The AFE incorporates a phase delay generator which
ensures that the two ADCs are converting the inputs
with a fixed delay between them. The two ADCs are
synchronously sampling, but the averaging of
modulator outputs is delayed so that the sinc filter
outputs (thus, the ADC outputs) show a fixed phase
delay, as determined by the PHASE register setting.
The PHASE register (PHASE<7:0>) is a 7-bit + sign,
MSB first, two’s complement register, that indicates
how much phase delay there is to be between
Channel 0 and Channel 1. The reference channel for
the delay is Channel 1 (typically the voltage channel for
power metering applications). When PHASE<7:0> bits
are positive, Channel 0 is lagging versus Channel 1.
When PHASE<7:0> are negative, Channel 0 is leading
versus Channel 1. The amount of delay between two
ADC conversions is given by the following formula:
EQUATION B-16:
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration with MCLK = 4 MHz.
The data ready signals are affected by the phase delay
settings. Typically, the time difference between the data
ready pulses of Channel 0 and Channel 1 is equal to
the phase delay setting.
B.4.9.1 Phase Delay Limits
The phase delay can only go from -OSR/2 to +OSR/2 – 1.
This sets the fine phase resolution. The PHASE register is
coded with 2’s complement.
If larger delays between the two channels are needed,
they can be implemented by the microcontroller. A
FIFO can save incoming data from the leading channel
for a number N of DRCLK clocks. In this case, DRCLK
would represent the coarse timing resolution, and
DMCLK the fine timing resolution. The total delay will
then be equal to:
Delay = N/DRCLK + PHASE/DMCLK
The Phase Delay register can be programmed once
with the OSR = 256 setting, and will adjust to the OSR
automatically afterwards, without the need to change
the value of the PHASE register.
• OSR = 256: the delay can go from -128 to +127.
PHASE<7> is the sign bit. PHASE<6> is the MSB
and PHASE<0> is the LSB.
• OSR = 128: the delay can go from -64 to +63.
PHASE<6> is the sign bit. PHASE<5> is the MSB
and PHASE<0> is the LSB.
• OSR = 64: the delay can go from -32 to +31.
PHASE<5> is the sign bit. PHASE<4> is the MSB
and PHASE<0> is the LSB.
• OSR = 32: the delay can go from -16 to +15.
PHASE<4> is the sign bit. PHASE<3> is the MSB
and PHASE<0> is the LSB.
Note: A detailed explanation of the Data Ready
pin (DR
) with phase delay is present in
Section B.5.9.1 “Data Ready Latches
And Data Ready Modes
(DRMODE<1:0>)”.
Delay
Phase Register Code
DMCLK
--------------------------------------------------=
TABLE B-10: PHASE VALUES WITH
MCLK = 4 MHZ, OSR = 256
PHASE Register Value Delay
(CH0 relative
to CH1)
Binary
Hex
01111111 0x7F +127 µs
01111110 0x7E +126 µs
00000001 0x01 +1 µs
00000000 0x00 0 µs
11111111 0xFF -1 µs
10000001 0x81 -127 µs
10000000 0x80 -128 µs