Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 447
PIC18F87J72 FAMILY
B.4.6 VOLTAGE REFERENCE
B.4.6.1 Internal Voltage Reference
The AFE contains an internal voltage reference source
specially designed to minimize drift over temperature.
In order to enable the internal voltage reference, the
VREFEXT bit in the Configuration register must be set
to ‘0’ (Default mode). This internal V
REF supplies refer-
ence voltage to both channels. The typical value of this
voltage reference is 2.37V ±2%. The internal reference
has a very low typical temperature coefficient of
±12 ppm/°C, allowing the output codes to have minimal
variation with respect to temperature since they are
proportional to (1/V
REF).
The noise of the internal voltage reference is low
enough not to significantly degrade the SNR of the
ADC if compared to a precision external low-noise
voltage reference.
The output pin for the internal voltage reference is
REFIN+/OUT.
When the internal voltage reference is enabled, the
REFIN- pin should always be connected to SAV
SS.
For optimal ADC accuracy, appropriate bypass
capacitors should be placed between REFIN+/OUT
and SAV
SS. Decoupling at the sampling frequency,
around 1 MHz is important, for any noise around this
frequency will be aliased back into the conversion data.
0.1 µF ceramic and 10 µF tantalum capacitors are
recommended.
These bypass capacitors are not mandatory for correct
ADC operation, but removing these capacitors may
degrade accuracy of the ADC. The bypass capacitors
also help for applications where the voltage reference
output is connected to other circuits. In this case,
additional buffering may be needed as the output drive
capability of this output is low.
B.4.6.2 Differential External Voltage Inputs
When the VREFEXT bit is high, the two reference pins
(REFIN+/OUT, REFIN-) become a differential voltage
reference input. The voltage at the REFIN+/OUT is
noted V
REF+ and the voltage at the REFIN- pin is noted
V
REF-. The differential voltage input value is given by
the following equation:
V
REF = VREF+ – VREF-
The specified V
REF range is from 2.2V to 2.6V. The
REFIN- pin voltage (V
REF-) should be limited to ±0.3V.
Typically, for single-ended reference applications, the
REFIN- pin should be directly connected to SAV
SS.
B.4.7 POWER-ON RESET
The AFE contains its own internal POR circuit that
monitors analog supply voltage AV
DD during operation.
The typical threshold for a power-up event detection is
4.2V, ±5%. The POR circuit has a built-in hysteresis for
improved transient spikes immunity that has a typical
value of 200 mV. Proper decoupling capacitors (0.1 µF
ceramic and 10 µF tantalum) should be mounted as
close as possible to the AV
DD pin, providing additional
transient immunity.
Figure B-4 illustrates the different conditions at
power-up and a power-down event in the typical
conditions. All internal DC biases are not settled until at
least 50 µs after system POR. Any DR
pulses during
this time after system Reset should be ignored. After
POR, DR pulses are present at the pin with all the
default conditions in the Configuration registers.
The analog and digital power supplies are indepen-
dent. Since AV
DD is the only power supply that is mon-
itored, it is highly recommended to power up DV
DD first
as a power-up sequence. If AV
DD is powered up first, it
is highly recommended to keep the RESET
pin low
during the whole power-up sequence.
FIGURE B-4: POWER-ON RESET
OPERATION
AVDD
5V
4.2V
4V
0V
Device
Mode
Reset
Proper
Operation
Reset
Time
50 µs
t
POR