Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 445
PIC18F87J72 FAMILY
The gain of the transfer function of this filter is 1 at each
multiple of DMCLK (typically 1 MHz), so a proper
anti-aliasing filter must be placed at the inputs to
attenuate the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple
first-order RC network with a sufficiently low time
constant to generate high rejection at DMCLK
frequency.
EQUATION B-13: SINC FILTER TRANSFER
FUNCTION H(z)
The Normal-Mode Rejection Ratio (NMRR) or gain of
the transfer function is given by the following equation:
EQUATION B-14: MAGNITUDE OF
FREQUENCY RESPONSE
H(f)
Figure B-3 shows the sinc filter frequency response:
FIGURE B-3: SINC FILTER RESPONSE
WITH MCLK = 4 MHZ,
OSR = 64, PRESCALE = 1
B.4.5 ADC OUTPUT CODING
The second-order modulator, SINC
3
filter, PGA, VREF
and analog input structure all work together to produce
the device transfer function for the analog to digital
conversion (see Equation B-15).
The channel data is either a 16-bit or 24-bit word,
presented in 23-bit or 15-bit plus sign, two’s
complement format and is MSB (left) justified.
The ADC data is two or three bytes wide depending on
the WIDTH bit of the associated channel. The 16-bit
mode includes a round to the closest 16-bit word
(instead of truncation) in order to improve the accuracy
of the ADC data.
In case of positive saturation (CHn+ – CHn- > V
REF/3),
the output is locked to 7FFFFF for 24-bit mode (7FFF
for 16-bit mode). In case of negative saturation
(CHn+ – CHn-  V
REF/3), the output code is locked to
800000 for 24-bit mode (8000 for 16-bit mode).
Equation B-15 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC
3
filter (see Equation B-13
and Equation B-14).
EQUATION B-15:
Hz
1z
OSR–
–
OSR 1 z
1–
–
---------------------------------



3
=
z
2fj
DMCLK
----------------------


exp=
where
NMRR f
c

f
DMCLK
----------------------



sin
c

f
DRCLK
--------------------



sin
----------------------------------------------
3
=
NMRR f
c 
f
f
S
----


sin
c 
f
f
D
-----


sin
-----------------------------
3
=
cxsin
xsin
x
---------------
=
or,
where
-120
-100
-80
-60
-40
-20
0
20
1 10 100 1000 10000 100000 1000000
Input Frequency (Hz)
Magnitude (dB)
DATA_CHn
CH
n+
CH
n-
–
V
REF+
V
REF-
–
--------------------------------------


8,388,608 G 3
 =
DATA_CHn
CH
n+
CH
n-
–
V
REF+
V
REF-
–
--------------------------------------


32 768,G3
 =
(For 24-bit Mode Or WIDTH = 1)
(For 16-bit Mode Or WIDTH = 0)