Datasheet

PIC18F87J72 FAMILY
DS39979A-page 444 Preliminary  2010 Microchip Technology Inc.
B.4.3 DELTA-SIGMA MODULATOR
B.4.3.1 Architecture
Both of the ADCs in the AFE are identical and they
include a second-order modulator with a multi-bit DAC
architecture (see Figure B-2). The quantizer is a Flash
ADC composed of 4 comparators with equally spaced
thresholds and a thermometer output coding. The
proprietary 5-level architecture ensures minimum
quantization noise at the outputs of the modulators
without disturbing linearity or inducing additional
distortion. The sampling frequency is DMCLK (typically
1 MHz with MCLK = 4 MHz) so the modulator outputs
are refreshed at a DMCLK rate.
Both modulators also include a dithering algorithm that
can be enabled through the DITHER<1:0> bits in the
Configuration register. This dithering process improves
THD and SFDR (for high OSR settings) while
increasing slightly the noise floor of the ADCs. For
power metering applications and applications that are
distortion-sensitive, it is recommended to keep
DITHER enabled for both ADCs. In the case of power
metering applications, THD and SFDR are critical
specifications to optimize SNR (noise floor). This is not
really problematic due to the large averaging factor at
the output of the ADCs; therefore, even for low OSR
settings, the dithering algorithm will show a positive
impact on the performance of the application.
Figure B-2 represents a simplified block diagram of the
Delta-Sigma ADC present on the AFE.
FIGURE B-2: SIMPLIFIED DELTA-SIGMA
ADC BLOCK DIAGRAM
B.4.3.2 Modulator Input Range and
Saturation Point
For a specified voltage reference value of 2.4V, the mod-
ulators’ specified differential input range is ±500 mV. The
input range is proportional to V
REF and scales according
to the V
REF voltage. This range ensures the stability of
the modulator over amplitude and frequency. Outside of
this range, the modulator is still functional, however, its
stability is no longer ensured, and therefore, it is not rec-
ommended to exceed this limit. The saturation point for
the modulator is V
REF/3 since the transfer function of the
ADC includes a gain of 3 by default (independent from
the PGA setting). See Section B.4.5 “ADC Output
Coding”.
B.4.3.3 Boost Mode
The Delta-Sigma modulators also include an
independent Boost mode for each channel. If the
corresponding BOOST<1:0> bit is enabled, the power
consumption of the modulator is multiplied by 2 and its
bandwidth is increased to be able to sustain AMCLK
clock frequencies, up to 8.192 MHz, while keeping the
ADC accuracy. When disabled, the power consumption
is back to normal and the AMCLK clock frequencies
can only reach up to 5 MHz without affecting ADC
accuracy.
B.4.4 SINC
3
FILTER
Both of the ADCs include a decimation filter that is a
third-order sinc (or notch) filter. This filter processes the
multi-bit bitstream into 16 or 24-bit words (depending
on the WIDTH Configuration bit). The settling time of
the filter is 3 DMCLK periods. It is recommended to dis-
card unsettled data to avoid data corruption, which can
be done easily by setting the DR_LTY bit high in the
STATUS/COM register.
The resolution achievable at the output of the sinc filter
(the output of the ADC) is dependant on the OSR and
is summarized with the following table:
For 24-Bit Output mode (WIDTH = 1), the output of the
sinc filter is padded with least significant zeros for any
resolution less than 24 bits.
For 16-Bit Output modes, the output of the sinc filter is
rounded to the closest 16-bit number in order to
conserve only 16-bit words and to minimize truncation
error.
Second
Order
Integrator
Loop
Filter
Quantizer
DAC
Differential
Voltage Input
Output
Bitstream
5-Level
Flash ADC
Delta-Sigma Modulator
TABLE B-5: ADC RESOLUTION vs. OSR
OSR<1:0> OSR
ADC Resolution (bits)
No Missing Codes
00 32 17
01 64 20
10 128 23
11 256 24