Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 443
PIC18F87J72 FAMILY
When an ADC exits ADC Shutdown mode, any phase
delay present before shutdown was entered will still be
present. If one ADC was not in shutdown, the ADC
leaving Shutdown mode will resynchronize
automatically the phase delay relative to the other ADC
channel per the Phase Delay register block and give
DR
pulses accordingly.
If an ADC is placed in Shutdown mode while the other
is converting, it is not shutting down the internal clock.
When going back out of shutdown, it will be
resynchronized automatically with the clock that did not
stop during Reset.
If both ADCs are in ADC Reset or ADC Shutdown
modes, the clock is no more distributed to the digital
core for low-power operation. Once any of the ADC is
back to normal operation, the clock is automatically
distributed again.
B.3.21 FULL SHUTDOWN MODE
The lowest power consumption can be achieved when
SHUTDOWN<1:0> = 11, VREFEXT = CLKEXT = 1.
This mode is called “Full Shutdown mode” and no ana-
log circuitry is enabled. In this mode, the POR SV
DD
monitoring circuit is also disabled. When the clock is
Idle (CLKIA = 0 or 1 continuously), no clock is propa-
gated throughout the chip. Both ADCs are in shutdown,
the internal voltage reference is disabled and the
internal oscillator is disabled.
The only circuit that remains active is the SPI interface,
but this circuit does not induce any static power
consumption. If SCK is Idle, the only current
consumption comes from the leakage currents induced
by the transistors and is less than 1 µA on each power
supply.
This mode can be used to power down the chip
completely and avoid power consumption when there
is no data to convert at the analog inputs. Any SCK or
MCLK edge coming, while on this mode, will induce
dynamic power consumption.
Once any of the SHUTDOWN, CLKEXT and VREFEXT
bits returns to ‘0’, the POR SV
DD monitoring block is
back to operation and SV
DD monitoring can take place.
B.4 Device Overview
B.4.1 ANALOG INPUTS (CHn+/-)
The analog inputs of the dual-channel AFE can be con-
nected directly to current and voltage transducers (such
as shunts, current transformers or Rogowski coils). Each
input pin is protected by specialized ESD structures that
are certified to pass 7 kV HBM and 400V MM contact
charge. These structures allow bipolar ±6V continuous
voltage, with respect to SAV
SS, to be present at their
inputs without the risk of permanent damage.
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin relative to SAV
SS should be maintained in the ±1V
range during operation in order to ensure the specified
ADC accuracy. The common-mode signals should be
adapted to respect both the previous conditions and
the differential input voltage range. For best
performance, the common-mode signals should be
maintained to SAV
SS.
B.4.2 PROGRAMMABLE GAIN
AMPLIFIERS (PGA)
The two Programmable Gain Amplifiers (PGAs) reside
at the front end of each Delta-Sigma ADC. They have
two functions: translate the common-mode of the input
from SAV
SS to an internal level between SAVSS and
SAV
DD, and amplify the input differential signal. The
translation of the common-mode does not change the
differential signal, but re-centers the common-mode so
that the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded. The PGA is
controlled by the
PGA_CHn<2:0> bits in the GAIN
register. Table B-4 represents the gain settings for the
PGA:
TABLE B-4: PGA CONFIGURATION
SETTING
PGA Gain
(PGA_CHn<2:0>)
Gain
V
IN Range
(V)
(V/V) (dB)
000 10±0.5
001 26±0.25
010 4 12 ±0.125
011 8 18 ±0.0625
100 16 24 ±0.03125
101 32 30 ±0.015625