Datasheet

PIC18F87J72 FAMILY
DS39979A-page 442 Preliminary  2010 Microchip Technology Inc.
B.3.17 CMRR
This is the ratio between a change in the
common-mode input voltage and the ADC output
codes. It measures the influence of the common-mode
input voltage on the ADC outputs.
The CMRR specification can be DC (the
common-mode input voltage is taking multiple DC
values) or AC (the common-mode input voltage is a
sine wave at a certain frequency with a certain
common-mode). In AC, the amplitude of the sine wave
is representing the change in the power supply.
It is defined as:
EQUATION B-12:
When VCM = (CHn+ + CHn-)/2, the common-mode
input voltage, and V
OUT is the equivalent input voltage
that is what the output code translates to with the ADC
transfer function. For the AFE, VCM varies from -1V to
+1V, and for the AC specification, a 50/60 Hz sine wave
is chosen centered around 0V with a 500 mV
amplitude.
B.3.18 ADC RESET MODE
ADC Reset mode (also called Soft Reset mode) can
only be entered through setting the RESET<1:0> bits
high in the Configuration register. This mode is defined
as the condition where the converters are active but
their output is forced to ‘0’.
The registers are not affected in this Reset mode and
retain their values.
The ADCs can immediately output meaningful codes
after leaving Reset mode (and after the sinc filter settling
time of 3/DRCLK). This mode is both entered and exited
through the setting of the bits in the Configuration
register.
Each converter can be placed in Soft Reset mode
independently. The Configuration registers are not
modified by the Soft Reset mode.
A data ready pulse will not be generated by any ADC
while in Reset mode.
When an ADC exits ADC Reset mode, any phase delay
present before Reset was entered will still be present.
If one ADC was not in Reset, the ADC leaving Reset
mode will automatically resynchronize the phase delay,
relative to the other ADC channel, per the Phase Delay
register block and give DR
pulses accordingly.
If an ADC is placed in Reset mode while the other is
converting, it is not shutting down the internal clock.
When going back out of Reset, it will be resynchronized
automatically with the clock that did not stop during
Reset.
If both ADCs are in Soft Reset or Shutdown modes, the
clock is no longer distributed to the digital core for
low-power operation. Once any of the ADC is back to
normal operation, the clock is automatically distributed
again.
B.3.19 HARD RESET MODE (ARESET = 0)
This mode is only available during a POR or when the
ARESET
pin is pulled low. The ARESET pin low state
places the device in a Hard Reset mode.
In this mode, all internal registers are reset to their
default state.
The DC biases for the analog blocks are still active (i.e.,
the AFE is ready to convert). However, this pin clears
all conversion data in the ADCs. The comparator
outputs of both ADCs are forced to their Reset state
(‘0011’). The SINC filters are all reset as well as their
double output buffers. See serial timing for minimum
pulse low time in Section 29.0 “Electrical
Characteristics” of the data sheet.
During a Hard Reset, no communication with the part is
possible. The digital interface is maintained in a Reset
state.
B.3.20 ADC SHUTDOWN MODE
ADC Shutdown mode is defined as a state where the
converters and their biases are off, consuming only
leakage current. After this is removed, start-up delay
time (SINC filter settling time will occur before
outputting meaningful codes). The start-up delay is
needed to power up all DC biases in the channel that
were in shutdown. This delay is the same than t
POR
and any DR pulse coming within this delay should be
discarded.
Each converter can be placed in Shutdown mode
independently. The CONFIG registers are not modified
by the Shutdown mode. This mode is only available
through programming of the SHUTDOWN<1:0> bits in
the CONFIG2 register.
The output data is flushed to all zeros while in ADC
shutdown. No data ready pulses are generated by any
ADC while in ADC Shutdown mode.
CMRR dB 20
 V
OUT
 V
CM
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