Datasheet

PIC18F87J72 FAMILY
DS39979A-page 438 Preliminary  2010 Microchip Technology Inc.
B.3 Terminology and Formulas
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
• MCLK – Master Clock
• AMCLK – Analog Master Clock
• DMCLK – Digital Master Clock
• DRCLK – Data Rate Clock
• OSR – Oversampling Ratio
• Offset Error
• Gain Error
• Integral Non-Linearity Error
• Signal-To-Noise Ratio (SNR)
• Signal-To-Noise Ratio And Distortion (SINAD)
• Total Harmonic Distortion (THD)
• Spurious-Free Dynamic Range (SFDR)
• Idle Tones
• Dithering
•Crosstalk
• PSRR
•CMRR
• ADC Reset Mode
• Hard Reset Mode (ARESET = 0)
• ADC Shutdown Mode
• Full Shutdown Mode
B.3.1 MCLK – MASTER CLOCK
This is the fastest clock present in the device. This is
the frequency of the clock input at the CLKIA.
B.3.2 AMCLK – ANALOG MASTER CLOCK
This is the clock frequency that is present on the analog
portion of the device, after prescaling has occurred via
the CONFIG1 PRESCALE<1:0> register bits. The ana-
log portion includes the PGAs and the two sigma-delta
modulators.
EQUATION B-1:
B.3.3 DMCLK – DIGITAL MASTER CLOCK
This is the clock frequency that is present on the digital
portion of the device, after prescaling and division by 4.
This is also the sampling frequency, that is the rate at
which the modulator outputs are refreshed. Each
period of this clock corresponds to one sample and one
modulator output.
EQUATION B-2:
B.3.4 DRCLK – DATA RATE CLOCK
This is the output data rate (i.e., the rate at which the
ADCs output new data). Each new data is signaled by
a data ready pulse on the DR pin.
This data rate is depending on the OSR and the
prescaler with the following formula:
EQUATION B-3:
Since this is the output data rate, and since the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
Table B-2 describes the various combinations of OSR
and PRESCALE and their associated AMCLK, DMCLK
and DRCLK rates.
AMCLK
MCLK
PRESCALE
-------------------------------
=
TABLE B-1: OVERSAMPLING RATIO
SETTINGS
PRESCALE
(CONFIG1<15:14>)
Analog Master Clock
Prescale
00AMCLK = MCLK/1 (default)
01 AMCLK = MCLK/2
10 AMCLK = MCLK/4
11 AMCLK = MCLK/8
DMCLK
AMCLK
4
---------------------
MCLK
4 PRESCALE

----------------------------------------==
DRCLK
DMCLK
OSR
----------------------
AMCLK
4OSR

---------------------
MCLK
4 OSR PRESCALE

-----------------------------------------------------------===