Datasheet

PIC18F87J72 FAMILY
DS39979A-page 436 Preliminary  2010 Microchip Technology Inc.
B.2 Pin Description
B.2.1 AFE RESET (ARESET)
This pin is active-low and places the AFE in a Reset
state when active.
When ARESET = 0, all registers are reset to their
default value, no communication can take place and no
clock is distributed to internal circuitry. This state is
equivalent to a POR state.
Since the default state of the ADCs is on, the analog
power consumption when ARESET
= 0 is equivalent to
when ARESET
= 1. Only the digital power consumption
is largely reduced because this current consumption is
essentially dynamic and is reduced drastically when
there is no clock running.
All the analog biases are enabled during a Reset, so
that the part is fully operational just after a ARESET
rising edge.
This input is Schmitt triggered.
B.2.2 DIGITAL VDD (SVDD)
SVDD is the power supply pin for the AFE’s digital cir-
cuitry. This pin requires appropriate bypass capacitors
and should be maintained between 2.7V and 5.5V for
specified operation.
B.2.3 ANALOG VDD (SAVDD)
AVDD is the power supply pin for the AFE’s analog cir-
cuitry. This pin requires appropriate bypass capacitors
and should be maintained to 5V ±10% for specified
operation.
B.2.4 ADC DIFFERENTIAL ANALOG
INPUTS (CHn+/CHn-)
CH0-/CH0+ and CH1-/CH1+ are the two fully differential,
analog voltage inputs for the Delta-Sigma ADCs.
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±500 mV/GAIN with
V
REF = 2.4V.
The maximum absolute voltage, with respect to SAV
SS,
for each CHn+/- input pin is ±1V with no distortion and
±6V with no breaking after continuous voltage.
B.2.5 ANALOG GROUND (SAVSS)
SAVss is the ground connection to internal analog
circuitry (ADCs, PGA, voltage reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as SV
SS, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this pin be tied to this
plane of the PCB. This plane should also reference all
other analog circuitry in the system.
B.2.6 NON-INVERTING REFERENCE
INPUT, INTERNAL REFERENCE
OUTPUT (REFIN+/OUT)
This pin is the non-inverting side of the differential
voltage reference input for both ADCs or the internal
voltage reference output.
When VREFEXT = 1, and an external voltage
reference source can be used, the internal voltage ref-
erence is disabled. When using an external differential
voltage reference, it should be connected to its V
REF+
pin. When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT = 0, the internal voltage reference is
enabled and connected to this pin through a switch.
This voltage reference has minimal drive capability, and
thus, needs proper buffering and bypass capacitances
(10 µF tantalum in parallel with 0.1 µF ceramic) if used
as a voltage source.
For optimal performance, bypass capacitances should
be connected between this pin and AGND at all times,
even when the internal voltage reference is used.
However, these capacitors are not mandatory to
ensure proper operation.
B.2.7 INVERTING REFERENCE INPUT
(REFIN-)
This pin is the inverting side of the differential voltage
reference input for both ADCs. When using an external
differential voltage reference, it should be connected to
its V
REF- pin. When using an external, single-ended
voltage reference, or when VREFEXT = 0 (default) and
using the internal voltage reference, this pin should be
directly connected to SAVss.
B.2.8 DIGITAL GROUND CONNECTION
(SV
SS)
SVss is the ground connection to internal digital
circuitry (SINC filters, oscillator, serial interface). To
ensure accuracy and noise cancellation, SVss must be
connected to the same ground as SAVss, preferably
with a star connection. If a digital ground plane is
available, it is recommended that this pin be tied to this
plane of the Printed Circuit Board (PCB). This plane
should also reference all other digital circuitry in the
system.
B.2.9 DATA READY (DR)
The Data Ready pin indicates if a new conversion
result is ready to be read. The default state of this pin
is high when DR_HIZN = 1 and is high impedance
when DR_HIZN = 0 (default). After each conversion is
finished, a low pulse will take place on the Data Ready
pin to indicate the conversion result is ready as an
interrupt. This pulse is synchronous with the master
clock and has a defined and constant width.