Datasheet

PIC18F87J72 FAMILY
DS39979A-page 434 Preliminary  2010 Microchip Technology Inc.
APPENDIX B: DUAL-CHANNEL,
24-BIT AFE
REFERENCE
B.1 Introduction
B.1.1 DESCRIPTION
The dual-channel Analog Front End (AFE) contains two
synchronous sampling Delta-Sigma Analog-to-Digital
Converters (ADC), two PGAs, phase delay compensa-
tion block, internal voltage reference, modulator output
block and high-speed 20 MHz SPI compatible serial
interface. The converters contain a proprietary dithering
algorithm for reduced Idle tones and improved THD.
The internal register map contains 24-bit wide ADC
data words, as well as six writable control registers to
program gain, oversampling ratio, phase, resolution,
dithering, shutdown, Reset and communication
features. The communication is largely simplified with
various continuous read modes that can be accessed
by the DMA of an external device, and with a separate
Data Ready (DR) pin that can directly be connected to
an IRQ input of an external microcontroller.
The AFE is capable of interfacing to a large variety of
voltage and current sensors, including shunts, current
transformers, Rogowski coils and Hall effect sensors.
B.1.2 DELTA-SIGMA ADC
ARCHITECTURE
The AFE incorporates two Delta-Sigma ADCs with a
multi-bit architecture. A Delta-Sigma ADC is an
oversampling converter that incorporates a built-in
modulator which is digitizing the quantity of charge
integrated by the modulator loop. The quantizer is the
block that is performing the analog-to-digital
conversion. The quantizer is typically 1-bit or a simple
comparator which helps to maintain the linearity
performance of the ADC (the DAC structure is in this
case inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The 5-level quantizer is a Flash ADC composed of
4 comparators, arranged with equally spaced thresh-
olds and a thermometer coding. The AFE also includes
proprietary, 5-level DAC architecture that is inherently
linear for improved THD figures.
B.1.3 FEATURES
• Two synchronous sampling 16/24-bit resolution
Delta-Sigma A/D Converters with proprietary
multi-bit architecture
• 91 dB SINAD, -104 dBc THD (up to 35
th
harmonic),
109 dB SFDR for each channel
• Programmable data rate of up to 64 ksps
• Ultra Low-Power Shutdown mode with <2 µA
• -133 dB crosstalk between the two channels
• Low drift internal voltage reference: 12 ppm/°C
• Differential voltage reference input pins
• High gain PGA on each channel (up to 32V/V)
• Phase delay compensation between the two
channels with 1 µs time resolution
• Separate modulator outputs for each channel
• High-speed addressable 20 MHz SPI interface
with Mode 0,0 and 1,1 compatibility
• Independent analog and digital power supplies
4.5V-5.5V SAV
DD, 2.7V-5.5V SVDD
• Low-power consumption (14 mW typical at 5V)
B.1.4 APPLICATIONS
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring