Datasheet

PIC18F87J72 FAMILY
DS39979A-page 426 Preliminary  2010 Microchip Technology Inc.
TABLE 29-27: DUAL-CHANNEL AFE SERIAL PERIPHERAL INTERFACE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at SAVDD = 4.5 to 5.5V,
DV
DD = 2.7 to 5.5V, -40°C < TA <+85°C, CLOAD = 30 pF.
Parameters Sym Min Typ Max Units Conditions
Serial Clock Frequency f
SCK
—
—
—
—
20
10
MHz
MHz
4.5 SVDD 5.5
2.7 SV
DD 5.5
CS
Setup Time t
CSS
25
50
—
—
—
—
ns
ns
4.5 SVDD 5.5
2.7 SV
DD 5.5
CS
Hold Time
t
CSH
50
100
—
—
—
—
ns
ns
4.5 SVDD 5.5
2.7 SV
DD 5.5
CS Disable Time t
CSD
50 — — ns —
Data Setup Time t
SU
5
10
—
—
—
—
ns
ns
4.5 SVDD 5.5
2.7 SV
DD 5.5
Data Hold Time t
HD
10
20
—
—
—
—
ns
ns
4.5 SVDD 5.5
2.7SV
DD 5.5
Serial Clock High Time t
HI
25
50
—
—
—
—
ns
ns
4.5SVDD 5.5
2.7 SV
DD 5.5
Serial Clock Low Time t
LO
25
50
—
—
—
—
ns
ns
4.5 DVDD 5.5
2.7 DV
DD 5.5
Serial Clock Delay Time t
CLD
50 — — ns
Serial Clock Enable Time t
CLE
50 — — ns
Output Valid from SCK Low t
DO
— — 50 ns 2.7 SVDD 5.5
Output hold time t
HO
0——ns(Note 1)
Output disable time t
DIS
—
—
—
—
25
50
ns
ns
4.5 SVDD 5.5
2.7 SV
DD 5.5 (Note 1)
Reset Pulse Width (RESET)t
MCLR
100 — — ns 2.7 SVDD 5.5
Data Transfer Time to DR (Data Ready) t
DODR
— — 50 ns 2.7 SVDD 5.5
Data Ready Pulse Low Time t
DRP
—1/DMCLK — µs2.7 SVDD 5.5
Schmitt Trigger High-Level Input
Voltage
V
IH1 0.7 SVDD —SVDD + 1 V
Schmitt Trigger Low-Level Input Voltage V
IL1 -0.3 — 0.2 SVDD V
Hysteresis of Schmitt Trigger Inputs
(all digital inputs)
VHYS 300 — — mV
Low-Level Output Voltage, SDOA Pin V
OL ——0.4VIOL = +2.5 mA, SVDD = 5.0V
Low-Level Output Voltage, DR Pin VOL —0.4VIOL = +1.25 mA, SVDD = 5.0V
High-Level Output Voltage, SDOA Pin VOH SVDD – 0.5 — — V IOH = -2.5 mA, SVDD = 5.0V
High-Level Output Voltage, DR Pin VOH SVDD – 0.5 — — V IOH = -1.25 mA, SVDD = 5.0V
Input Leakage Current I
LI ——±1µACSA = SVDD, VIN = SVSS
or SV
DD
Output Leakage Current ILO ——±1µACSA = SVDD, VOUT = SVSS
or SV
DD
Internal Capacitance (all inputs and
outputs)
CINT ——7pFTA = 25°C,
SCKA = 1.0 MHz,
SVDD = 5.0V (Note 1)
Note 1: This parameter is periodically sampled and is not 100% tested.