Datasheet

PIC18F87J72 FAMILY
DS39979A-page 418 Preliminary  2010 Microchip Technology Inc.
FIGURE 29-15: MSSP I
2
C™ BUS START/STOP BITS TIMING WAVEFORMS
TABLE 29-20: MSSP I
2
C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 29-16: MSSP I
2
C™ BUS DATA TIMING
Param.
No.
Symbol Characteristic Min Max Units Conditions
90 T
SU:STA Start Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeated Start
condition
400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1,2)
2(TOSC)(BRG + 1) —
91 T
HD:STA Start Condition
Hold Time
100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
first clock pulse is
generated
400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1,2)
2(TOSC)(BRG + 1) —
92 T
SU:STO Stop Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) — ns
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1,2)
2(TOSC)(BRG + 1) —
93 T
HD:STO Stop Condition
Hold Time
100 kHz mode 2(TOSC)(BRG + 1) — ns
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1,2)
2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I
2
C™ pins.
2: F
OSC must be at least 16 MHz for I
2
C bus operation at this speed.
Note: Refer to Figure 29-3 for load conditions.
91
93
SCL
SDA
Start
Condition
Stop
Condition
90
92
Note: Refer to Figure 29-3 for load conditions.
90
91 92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out