Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 415
PIC18F87J72 FAMILY
FIGURE 29-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 29-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
 to SCK  or SCK  Input 3 TCY —ns
70A TSSL2WB SS to Write to SSPBUF 3 TCY —ns
71 TSCH SCK Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TDOR SDO Data Output Rise Time — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS  to SDO Output High-Impedance 10 50 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 TSCF SCK Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
82 T
SSL2DOV SDO Data Output Valid after SS  Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SS
 after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
74
75, 76
MSb bit 6 - - - - - - 1 LSb
77
bit 6 - - - - 1 LSb In
80
83
Note: Refer to Figure 29-3 for load conditions.
MSb In