Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 413
PIC18F87J72 FAMILY
FIGURE 29-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 29-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A T
B2B Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TDOR SDO Data Output Rise Time — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
81 TDOV2SCH,
T
DOV2SCL
SDO Data Output Setup to SCK Edge T
CY —ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
74
75, 76
78
80
MSb
79
73
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 29-3 for load conditions.
MSb In