Datasheet

PIC18F87J72 FAMILY
DS39979A-page 412 Preliminary  2010 Microchip Technology Inc.
FIGURE 29-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 29-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 T
DOR SDO Data Output Rise Time — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
78 TSCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
Note 1: Requires the use of Parameter #73A.
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
73
74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
Note: Refer to Figure 29-3 for load conditions.
MSb In