Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 407
PIC18F87J72 FAMILY
TABLE 29-8: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V)
TABLE 29-9: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
F10 F
OSC Oscillator Frequency Range 4 — 10 MHz HS mode only
F11 F
SYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only
F12 t
rc
PLL Start-up Time (Lock Time) — — 2 ms
F13 CLK CLKO Stability (Jitter) -2 — +2 %
† Data in “Typ” column is at 3.3V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
PIC18F87J72 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  T
A  +85°C for industrial
Param
No.
Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz
(1)
All Devices -2 +/-1 2 % +25°C VDD = 2.7-3.3V
-5 — 5 % -10°C to +85°C V
DD = 2.0-3.3V
-10 +/-1 10 % -40°C to +85°C VDD = 2.0-3.3V
INTRC Accuracy @ Freq = 31 kHz
(1)
All Devices 21.7 — 40.3 kHz -40°C to +85°C VDD = 2.0-3.3V
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given
time. When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’,
use the INTRC accuracy specification.