Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 327
PIC18F87J72 FAMILY
26.3 On-Chip Voltage Regulator
All of the PIC18F87J72 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F87J72 family incorporate
an on-chip regulator that allows the device to run its
core logic from V
DD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other V
DD pins. When
the regulator is enabled, a low-ESR filter capacitor
must be connected to the VDDCORE/VCAP pin
(Figure 26-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 29.3 “DC Characteristics:
PIC18F87J72 Family (Industrial)”.
If ENVREG is tied to V
SS, the regulator is disabled. In
this case, separate power for the core logic, at a nomi-
nal 2.5V, must be supplied to the device on the
V
DDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the V
DDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 26-2 for possible
configurations.
26.3.1 VOLTAGE REGULATION AND
LOW-VOLTAGE DETECTION
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s V
DDMAX. It
does not have the capability to boost V
DD levels below
2.5V.
In order to prevent “brown-out” conditions, when the
voltage drops too low for the regulator, the regulator
enters Tracking mode. In Tracking mode, the regulator
output follows V
DD, with a typical voltage drop of
100 mV.
The on-chip regulator includes a simple Low-Voltage
Detect (LVD) circuit. If V
DD drops too low to maintain
approximately 2.45V on V
DDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>),
and clears the REGSLP (WDTCON<7>) bit if it was set.
This can be used to generate an interrupt and puts the
application into a low-power operational mode or
triggers an orderly shutdown. Low-Voltage Detection is
only available when the regulator is enabled.
FIGURE 26-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
VDD
ENVREG
V
DDCORE/VCAP
VSS
3.3V
(1)
2.5V
(1)
VDD
ENVREG
V
DDCORE/VCAP
VSS
CF
3.3V
Regulator Enabled (ENVREG tied to VDD):
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
V
DDCORE/VCAP
VSS
2.5V
(1)
Regulator Disabled (VDD tied to VDDCORE):
Note 1: These are typical operating voltages. For
the full operating ranges of V
DD and
V
DDCORE, refer to Section 29.1 “DC
Characteristics: Supply Voltage
PIC18F87J72 Family (Industrial)”.
PIC18F87J72
PIC18F87J72
PIC18F87J72