Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 80 (12x12) 8-Bit 48 MHz I/O number 51

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Table Of Contents

Analog Features:
LCD Driver and Keypad Interface Features:
Flexible Oscillator Structure:
Low-Power Features:
Peripheral Highlights:
Special Microcontroller Features:
Target Applications:
Pin Diagram
Typical Application Circuit: Single-Phase Power Meter
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 Core Features
- 1.2 Analog Features
- 1.3 LCD Driver
- 1.4 Other Special Features
- 1.5 Details on Individual Family Members
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers
- 2.1 Basic Connection Requirements
  - FIGURE 2-1: Recommended Minimum connections
- 2.2 Power Supply Pins
  - 2.2.1 Decoupling Capacitors
  - 2.2.2 Tank Capacitors
- 2.3 Master Clear (MCLR) Pin
  - FIGURE 2-2: Example of MCLR Pin Connections
- 2.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)
  - FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap
- 2.5 ICSP Pins
- 2.6 External Oscillator Pins
- 2.7 Unused I/Os
  - FIGURE 2-4: Suggested Placement of the Oscillator Circuit
3.0 Oscillator Configurations
- 3.1 Oscillator Types
  - FIGURE 3-1: PIC18F87J72 Family Clock Diagram
- 3.2 Control Registers
  - Register 3-1: OSCCON: Oscillator Control Register(1)
  - Register 3-2: OSCTUNE: Oscillator Tuning Register
- 3.3 Clock Sources and Oscillator Switching
  - 3.3.1 Clock Source Selection
  - 3.3.2 Oscillator Transitions
- 3.4 External Oscillator Modes
- 3.5 Internal Oscillator Block
- 3.6 Effects of Power-Managed Modes on the Various Clock Sources
- 3.7 Power-up Delays
  - TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode
4.0 Power-Managed Modes
- 4.1 Selecting Power-Managed Modes
- 4.2 Run Modes
- 4.3 Sleep Mode
- 4.4 Idle Modes
- 4.5 Exiting Idle and Sleep Modes
5.0 Reset
- 5.1 RCON Register
  - FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit
  - Register 5-1: RCON: Reset Control Register
- 5.2 Master Clear (MCLR)
- 5.3 Power-on Reset (POR)
- 5.4 Brown-out Reset (BOR)
  - FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
  - 5.4.1 Detecting BOR
- 5.5 Configuration Mismatch (CM)
- 5.6 Power-up Timer (PWRT)
  - 5.6.1 Time-out Sequence
- 5.7 Reset State of Registers
  - TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register
  - TABLE 5-2: Initialization Conditions for All Registers
6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Program Memory and the Extended Instruction Set
- 6.6 Data Memory and the Extended Instruction Set
7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
  - FIGURE 7-1: TABLE READ Operation
  - FIGURE 7-2: Table Write Operation
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
  - FIGURE 7-4: Reads from Flash Program Memory
  - EXAMPLE 7-1: Reading a Flash Program Memory Word
- 7.4 Erasing Flash Program Memory
  - 7.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 7-2: Erasing Flash Program Memory
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
  - TABLE 7-2: Registers Associated with Program Flash Memory
8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
9.0 Interrupts
- FIGURE 9-1: PIC18F87J72 Family Interrupt Logic
- 9.1 INTCON Registers
- 9.2 PIR Registers
- 9.3 PIE Registers
- 9.4 IPR Registers
- 9.5 RCON Register
  - Register 9-13: RCON: Reset Control Register
- 9.6 INTx Pin Interrupts
- 9.7 TMR0 Interrupt
- 9.8 PORTB Interrupt-on-Change
- 9.9 Context Saving During Interrupts
  - EXAMPLE 9-1: Saving STATUS, WREG and BSR Registers in RAM
10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 I/O Port Pin Capabilities
- 10.2 PORTA, TRISA and LATA Registers
- 10.3 PORTB, TRISB and LATB Registers
- 10.4 PORTC, TRISC and LATC Registers
- 10.5 PORTD, TRISD and LATD Registers
- 10.6 PORTE, TRISE and LATE Registers
- 10.7 PORTF, LATF and TRISF Registers
- 10.8 PORTG, TRISG and LATG Registers
11.0 Timer0 Module
- Register 11-1: T0CON: Timer0 Control Register
- 11.1 Timer0 Operation
- 11.2 Timer0 Reads and Writes in 16-Bit Mode
  - FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)
  - FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)
- 11.3 Prescaler
  - 11.3.1 Switching Prescaler Assignment
- 11.4 Timer0 Interrupt
  - TABLE 11-1: Registers Associated with Timer0
12.0 Timer1 Module
- Register 12-1: T1CON: Timer1 Control Register
- 12.1 Timer1 Operation
  - FIGURE 12-1: Timer1 Block Diagram (8-Bit Mode)
  - FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
- 12.2 Timer1 16-Bit Read/Write Mode
- 12.3 Timer1 Oscillator
- 12.4 Timer1 Interrupt
- 12.5 Resetting Timer1 Using the CCP Special Event Trigger
- 12.6 Using Timer1 as a Real-Time Clock
  - EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
  - TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
13.0 Timer2 Module
- 13.1 Timer2 Operation
  - Register 13-1: T2CON: Timer2 Control Register
- 13.2 Timer2 Interrupt
- 13.3 Timer2 Output
  - FIGURE 13-1: Timer2 Block Diagram
  - TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
14.0 Timer3 Module
- Register 14-1: T3CON: Timer3 Control Register
- 14.1 Timer3 Operation
  - FIGURE 14-1: Timer3 Block Diagram (8-Bit Mode)
  - FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
- 14.2 Timer3 16-Bit Read/Write Mode
- 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source
- 14.4 Timer3 Interrupt
- 14.5 Resetting Timer3 Using the CCP Special Event Trigger
  - TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
15.0 Real-Time Clock and Calendar (RTCC)
- FIGURE 15-1: RTCC Block Diagram
- 15.1 RTCC Module Registers
- RTCC Control Registers
- RTCC Value Registers
- Alarm Value Registers
- 15.2 Operation
- 15.3 Alarm
  - 15.3.1 Configuring the Alarm
    - FIGURE 15-5: Alarm Mask Settings
  - 15.3.2 Alarm Interrupt
    - FIGURE 15-6: Timer Pulse Generation
- 15.4 Sleep Mode
- 15.5 Reset
  - 15.5.1 Device Reset
  - 15.5.2 Power-on Reset (POR)
- 15.6 Register Maps
16.0 Capture/Compare/PWM (CCP) Modules
- Register 16-1: CCPxCON: CCPx Control Register (CCP1, CCP2 Modules)
- 16.1 CCP Module Configuration
- 16.2 Capture Mode
- 16.3 Compare Mode
- 16.4 PWM Mode
17.0 Liquid Crystal Display (LCD) Driver Module
- FIGURE 17-1: LCD Driver Module Block Diagram
- 17.1 LCD Registers
  - 17.1.1 LCD Control Registers
  - 17.1.2 LCD Data Registers
    - Register 17-4: LCDDATAx: LCD Data Registers(1)
    - TABLE 17-2: LCDDATA Registers and Bits for Segment and COM Combinations
- 17.2 LCD Clock Source
  - 17.2.1 LCD Voltage Regulator Clock Source
  - 17.2.2 Clock sOURCE cONSIDERATIONS
    - FIGURE 17-2: LCD Clock Generation
- 17.3 LCD Bias Generation
- 17.4 LCD Multiplex Types
  - TABLE 17-3: PORTE<6:4> Function
- 17.5 Segment Enables
- 17.6 Pixel Control
- 17.7 LCD Frame Frequency
  - TABLE 17-4: Frame Frequency Formulas
  - TABLE 17-5: Approximate Frame Frequency (in Hz) for LP Prescaler Settings
- 17.8 LCD Waveform Generation
- 17.9 LCD Interrupts
  - FIGURE 17-17: Example Waveforms and Interrupt Timing in Quarter Duty Cycle Drive
- 17.10 Operation During Sleep
  - 17.10.1 Using the LCD Regulator During Sleep
    - FIGURE 17-18: Sleep Entry/Exit When SLPEN = 1 or CS<1:0> = 00
- 17.11 Configuring the LCD Module
  - TABLE 17-6: Registers Associated with LCD Operation
18.0 Master Synchronous Serial Port (MSSP) Module
- 18.1 Master SSP (MSSP) Module Overview
- 18.2 Control Registers
- 18.3 SPI Mode
- 18.4 I2C Mode
19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 19.1 Control Registers
- 19.2 EUSART Baud Rate Generator (BRG)
- 19.3 EUSART Asynchronous Mode
- 19.4 EUSART Synchronous Master Mode
  - 19.4.1 EUSART Synchronous Master Transmission
  - 19.4.2 EUSART Synchronous Master Reception
    - FIGURE 19-13: Synchronous Reception (Master Mode, SREN)
    - TABLE 19-8: Registers Associated with Synchronous Master Reception
- 19.5 EUSART Synchronous Slave Mode
  - 19.5.1 EUSART Synchronous Slave Transmit
    - TABLE 19-9: Registers Associated with Synchronous Slave Transmission
  - 19.5.2 EUSART Synchronous Slave Reception
    - TABLE 19-10: Registers Associated with Synchronous Slave Reception
20.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)
- 20.1 Control Registers
  - Register 20-1: TXSTA2: AUSART Transmit Status and Control Register
  - Register 20-2: RCSTA2: ausart Receive Status and Control Register
- 20.2 AUSART Baud Rate Generator (BRG)
  - 20.2.1 Operation in Power-Managed Modes
  - 20.2.2 Sampling
- 20.3 AUSART Asynchronous Mode
- 20.4 AUSART Synchronous Master Mode
  - 20.4.1 AUSART Synchronous Master Transmission
  - 20.4.2 AUSART Synchronous Master Reception
    - FIGURE 20-8: Synchronous Reception (Master Mode, SREN)
    - TABLE 20-7: Registers Associated with Synchronous Master Reception
- 20.5 AUSART Synchronous Slave Mode
  - 20.5.1 AUSART Synchronous Slave Transmit
    - TABLE 20-8: Registers Associated with Synchronous Slave Transmission
  - 20.5.2 AUSART Synchronous Slave Reception
    - TABLE 20-9: Registers Associated with Synchronous Slave Reception
21.0 12-Bit Analog-to-Digital Converter (A/D) Module
- Register 21-1: ADCON0: A/D Control Register 0
- Register 21-2: ADCON1: A/D Control Register 1
- Register 21-3: ADCON2: A/D Control Register 2
- FIGURE 21-1: A/D Block Diagram(1,2)
- FIGURE 21-2: Analog Input Model
- 21.1 A/D Acquisition Requirements
- 21.2 Selecting and Configuring Automatic Acquisition Time
- 21.3 Selecting the A/D Conversion Clock
  - TABLE 21-1: Tad vs. Device Operating Frequencies
- 21.4 Configuring Analog Port Pins
- 21.5 A/D Conversions
- 21.6 Use of the CCP2 Trigger
  - FIGURE 21-1: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
  - FIGURE 21-2: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
- 21.7 A/D Converter Calibration
- 21.8 Operation in Power-Managed Modes
  - TABLE 21-2: Summary of A/D Registers
22.0 Dual-Channel, 24-Bit Analog Front End (AFE)
- FIGURE 22-1: Dual-Channel Analog Front End Functional Diagram
- 22.1 Functional Overview
- 22.2 AFE Register Map
  - TABLE 22-1: AFE Register map
  - TABLE 22-2: Register Map Grouping for Continuous read modes
- 22.3 Serial Interface
- 22.4 AFE Connections
- 22.5 Using the AFE
23.0 Comparator Module
- Register 23-1: CMCON: Comparator Module Control Register
- 23.1 Comparator Configuration
  - FIGURE 23-1: Comparator I/O Operating Modes
- 23.2 Comparator Operation
- 23.3 Comparator Reference
- 23.4 Comparator Response Time
- 23.5 Comparator Outputs
  - FIGURE 23-3: Comparator Output Block Diagram
- 23.6 Comparator Interrupts
- 23.7 Comparator Operation During Sleep
- 23.8 Effects of a Reset
- 23.9 Analog Input Connection Considerations
  - FIGURE 23-4: Comparator Analog Input Model
  - TABLE 23-1: Registers Associated with Comparator Module
24.0 Comparator Voltage Reference Module
- 24.1 Configuring the Comparator Voltage Reference
  - Register 24-1: CVRCON: Comparator Voltage Reference Control Register
  - FIGURE 24-1: Comparator Voltage Reference Block Diagram
- 24.2 Voltage Reference Accuracy/Error
- 24.3 Operation During Sleep
- 24.4 Effects of a Reset
- 24.5 Connection Considerations
  - FIGURE 24-2: Comparator Voltage Reference Output Buffer Example
  - TABLE 24-1: Registers Associated with Comparator Voltage Reference
25.0 Charge Time Measurement Unit (CTMU)
- FIGURE 25-1: CTMU Block Diagram
- 25.1 CTMU Operation
- 25.2 CTMU Module Initialization
- 25.3 Calibrating the CTMU Module
  - 25.3.1 Current Source Calibration
  - 25.3.2 Capacitance Calibration
    - EXAMPLE 25-3: Capacitance Calibration Routine
- 25.4 Measuring Capacitance with the CTMU
  - 25.4.1 Absolute Capacitance Measurement
  - 25.4.2 Relative Charge Measurement
    - EXAMPLE 25-4: Routine for Capacitive Touch Switch
- 25.5 Measuring Time with the CTMU Module
  - FIGURE 25-3: Typical Connections and Internal Configuration for Time Measurement
- 25.6 Creating a Delay with the CTMU Module
  - FIGURE 25-4: Typical Connections and Internal Configuration for Pulse Delay Generation
- 25.7 Operation During Sleep/Idle Modes
  - 25.7.1 Sleep Mode and Deep Sleep Modes
  - 25.7.2 Idle Mode
- 25.8 Effects of a Reset on CTMU
- 25.9 Registers
26.0 Special Features of the CPU
- 26.1 Configuration Bits
  - 26.1.1 Considerations for Configuring PIC18F87J72 Family Devices
- 26.2 Watchdog Timer (WDT)
  - 26.2.1 Control Register
- 26.3 On-Chip Voltage Regulator
- 26.4 Two-Speed Start-up
  - FIGURE 26-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)
  - 26.4.1 Special Considerations for Using Two-Speed Start-up
- 26.5 Fail-Safe Clock Monitor
- 26.6 Program Verification and Code Protection
  - 26.6.1 Configuration Register Protection
- 26.7 In-Circuit Serial Programming
- 26.8 In-Circuit Debugger
  - TABLE 26-4: Debugger Resources
27.0 Instruction Set Summary
- 27.1 Standard Instruction Set
- 27.2 Extended Instruction Set
28.0 Development Support
- 28.1 MPLAB Integrated Development Environment Software
- 28.2 MPLAB C Compilers for Various Device Families
- 28.3 HI-TECH C for Various Device Families
- 28.4 MPASM Assembler
- 28.5 MPLINK Object Linker/ MPLIB Object Librarian
- 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 28.7 MPLAB SIM Software Simulator
- 28.8 MPLAB REAL ICE In-Circuit Emulator System
- 28.9 MPLAB ICD 3 In-Circuit Debugger System
- 28.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 28.12 MPLAB PM3 Device Programmer
- 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
29.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
  - FIGURE 29-1: Voltage-frequency Graph, Regulator Enabled (Industrial)(1)
  - FIGURE 29-2: Voltage-frequency Graph, Regulator Disabled (Industrial)(1,2)
- 29.1 DC Characteristics: Supply Voltage PIC18F87J72 Family (Industrial)
- 29.2 DC Characteristics: Power-Down and Supply Current PIC18F87J72 Family (Industrial)
- 29.3 DC Characteristics: PIC18F87J72 Family (Industrial)
- 29.4 DC Characteristics: CTMU Current Source Specifications
- 29.5 AC (Timing) Characteristics
30.0 Packaging Information
- 30.1 Package Marking Information
- 30.2 Package Details
Appendix A: Revision History
- Revision A (June 2010)
Appendix B: Dual-Channel, 24-Bit AFE Reference
- TABLE B-1: OVERSAMPLING RATIO SETTINGS
- TABLE B-2: Device data rates in function of mclk, osr AND PRESCALE
- TABLE B-3: OVERSAMPLING RATIO SETTINGS
- Step 1
- Step 2
INDEX
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 2010 Microchip Technology Inc. Preliminary DS39979A-page 301

PIC18F87J72 FAMILY

FIGURE 24-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 24-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51

CMCON

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51

TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.

CVREF Output

–

CVREF

Module

Voltage

Reference

Output

Impedance

(1)

RF5

Note 1: R is dependent upon the Comparator Voltage Reference bits, CVRCON<5> and CVRCON<3:0>.

PIC18F87J72