Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 287
PIC18F87J72 FAMILY
22.4 AFE Connections
The dual-channel AFE has multiple data and power con-
nections that are independent of the digital side of the
microcontroller. These connections are required to use
the AFE, and are in addition to the connection and layout
connections provided in Section 2.0 “Guidelines for
Getting Started with PIC18FJ Microcontrollers”.
All of the connections required for proper operation of
the AFE are shown in Figure 22-3.
22.4.1 VOLTAGE AND GROUND
CONNECTIONS
The AFE has independent voltage supply requirements
that differ from the rest of the microcontroller. Digital cir-
cuits are supplied through the SVDD pin, which requires
a voltage of 2.7V to 5.5V. Typically, SV
DD can be tied to
3.3V, the same as the V
DD and AVDD pins. Analog cir-
cuits are separately supplied through the SAV
DD pin,
which requires a voltage of 4.5V to 5.5V (5V ±10%).
Independent ground returns are provided through the
SVss and SAVss pins, respectively.
As with the microcontroller’s V
DD/VSS and AVDD/AVSS
pins, bypass capacitors are required on the AFE power
and return pin pairs. Requirements for these capacitors
are identical to those for the V
DD/VSS and AVDD/AVSS
pins.
It is recommended that designs using PIC18F87J72
family devices incorporate a separate ground return
path for analog circuits. SAVss, as well as other AFE
analog pins (e.g., REFIN-) that require grounding,
should be tied to this analog return. SV
SS can be tied to
the digital ground, along with V
SS and AVSS. The ana-
log and digital grounds may be tied to a single point at
the power source.
FIGURE 22-3: REQUIRED CONNECTIONS FOR AFE OPERATION
PIC18F8XJ72
SDIA
GPIO
(1)
SDO
SDI
CH1-
SAVSS REFIN+/OUT REFIN- DR
SCKA
SDOA
Key (all values are recommendations):
C1 and C2: 0.1 F, 20V ceramic
C3 and C4: 100 nF, 20V ceramic.
Bold lines show SPI connections.
Note 1: Any available I/O pins may be used to control ARESET
and CSA. The software examples discussed in this chapter
use RD0 and RD7, respectively.
2: The software examples discussed in this chapter use CCP1 to generate the AFE clock source. Other clock sources
may be used, as required.
GPIO
(1)
ARESET
CSA
INT0
SCK
CCP1
(2)
CLKIA
C3 C4
CH1+
CH0-
CH0+
Differential
Analog
Inputs
SVSS SAVDD SVDD
C1
C2
Analog GND
SV
DD (3.3V)
SAV
DD (5V)