Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 281
PIC18F87J72 FAMILY
21.7 A/D Converter Calibration
The A/D Converter in the PIC18F87J72 family of
devices includes a self-calibration feature which
compensates for any offset generated within the
module. The calibration process is automated and is
initiated by setting the ADCAL bit (ADCON0<7>). The
next time the GO/DONE
bit is set, the module will per-
form a “dummy” conversion (which means it is reading
none of the input channels) and store the resulting value
internally to compensate for the offset. Thus,
subsequent offsets will be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
21.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. If desired, the device may be placed into
the corresponding power-managed Idle mode during
the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in Sleep mode requires the A/D RC clock to
be selected. If bits, ACQT<2:0>, are set to ‘000’ and a
conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCSx bits in the OSCCON register must have already
been cleared prior to starting the conversion.
TABLE 21-2: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 —ADIFRC1IF TX1IF SSPIF — TMR2IF TMR1IF 52
PIE1
—ADIERC1IE TX1IE SSPIE — TMR2IE TMR1IE 52
IPR1 —ADIPRC1IP TX1IP SSPIP — TMR2IP TMR1IP 52
PIR3 — LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52
PIE3
— LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52
IPR3 — LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52
ADRESH A/D Result Register High Byte 51
ADRESL A/D Result Register Low Byte 51
ADCON0 ADCAL
— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 51
ADCON1 TRIGSEL — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 51
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53
PORTA RA7
(1)
RA6
(1)
RA5 RA4 RA3 RA2 RA1 RA0 52
TRISA TRISA7
(1)
TRISA6
(1)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 52
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1
—52
TRISF TRISF5 TRISF4 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.