Datasheet

PIC18F87J72 FAMILY
DS39979A-page 248 Preliminary  2010 Microchip Technology Inc.
19.3 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA1<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTA1<2> and BAUDCON1<3>).
Parity is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
19.3.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 19-3. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG1 register (if available).
Once the TXREG1 register transfers the data to the
TSR register (occurs in one T
CY), the TXREG1 register
is empty and the TX1IF flag bit (PIR1<4>) is set. This
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF
will be set regardless of the state of TX1IE; it cannot be
cleared in software. TX1IF is also not cleared immedi-
ately upon loading TXREG1, but becomes valid in the
second instruction cycle following the load instruction.
Polling TX1IF immediately following a load of TXREG1
will return invalid results.
While TX1IF indicates the status of the TXREG1
register, another bit, TRMT (TXSTA1<1>), shows the
status of the TSR register. TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9; can be used as address/data bit.
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX1IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG1 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-3: EUSART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit, TX1IF, is set when enable bit,
TXEN, is set.
TX1IF
TX1IE
Interrupt
TXEN
Baud Rate CLK
SPBRG1
Baud Rate Generator
TX9D
MSb
LSb
Data Bus
TXREG1 Register
TSR Register
(8)
0
TX9
TRMT
SPEN
TX1 Pin
Pin Buffer
and Control
8

SPBRGH1
BRG16