Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 209
PIC18F87J72 FAMILY
18.4.2 OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I
2
C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I
2
C modes to be selected:
•I
2
C Master mode,
clock = (F
OSC/4) x (SSPADD + 1)
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
•I
2
C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
•I
2
C Firmware Controlled Master mode,
slave is Idle
Selection of any I
2
C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.
18.4.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I
2
C Slave mode hardware will always generate an
interrupt on an exact address match. In addition,
address masking will also allow the hardware to gener-
ate an interrupt for more than one address (up to 31 in
7-bit addressing and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK
) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK
pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit, SSPIF, is set. The BF bit is
cleared by reading the SSPBUF register, while bit,
SSPOV, is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
2
C specification, as well as the requirement of the
MSSP module, are shown in timing Parameter 100 and
Parameter 101.
18.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition, the
8 bits are shifted into the SSPSR register. All incoming
bits are sampled with the rising edge of the clock (SCL)
line. The value of register, SSPSR<7:1>, is compared to
the value of the SSPADD register. The address is com-
pared on the falling edge of the eighth clock (SCL) pulse.
If the addresses match and the BF and SSPOV bits are
clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK
pulse is generated.
4. The MSSP Interrupt Flag bit, SSPIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit, R/W
(SSPSTAT<2>), must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
addressing is as follows, with steps 7 through 9 for the
slave-transmitter:
1. Receive first (high) byte of address (SSPIF, BF
and UA bits (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears UA bit and releases the
SCL line).
3. Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear UA bit.
6. Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (SSPIF and
BF bits are set).
9. Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.