Datasheet

PIC18F87J72 FAMILY
DS39979A-page 20 Preliminary  2010 Microchip Technology Inc.
RESET 69 I ST AFE Master Reset logic input pin.
SVDD 70 P — AFE digital power supply pin.
SAVDD 74 P — AFE analog power supply reference pin.
CH0+ 1 I Analog Channel 0 non-inverting analog input pin.
CH0- 2 I Analog Channel 0 inverting analog input pin.
CH1- 19 I Analog Channel 1 inverting analog input pin.
CH1+ 20 I Analog Channel 1 Non-Inverting Analog Input Pin
SAV
SS 26 P — AFE analog ground pin (return path for analog circuitry).
REFIN+/OUT
REFIN+
REFOUT
28
I
O
Analog
Analog
AFE non-inverting voltage reference input.
Internal reference output pin.
REFIN- 29 I Analog Inverting voltage reference input pin.
SV
SS 36 P — AFE digital ground pin (return path for digital circuitry).
DR
40 — AFE data ready signal output pin.
CLKIA 41 I CMOS AFE oscillator crystal connection pin or external clock input pin.
CSA
58 I TTL AFE serial interface chip select pin.
SCKA 59 I TTL AFE serial interface clock pin.
SDOA 60 O TTL AFE serial interface data output pin.
SDIA 64 I TTL AFE serial interface data input pin.
TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I2C = I
2
C/SMBus compatible input OD = Open-Drain (no P diode to VDD)
I = Input O = Output
P= Power
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.