Datasheet

 2010 Microchip Technology Inc. Preliminary DS39979A-page 195
PIC18F87J72 FAMILY
18.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
18.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
2
C™)
- Full Master mode
- Slave mode (with general address call)
The I
2
C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
18.2 Control Registers
Each MSSP module has three associated control
registers. These include a status register (SSPSTAT)
and two control registers (SSPCON1 and SSPCON2).
The use of these registers and their individual bits differ
significantly depending on whether the MSSP module
is operated in SPI or I
2
C mode.
Additional details are provided under the individual
sections.
18.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO/SEG12
• Serial Data In (SDI) – RC4/SDI/SDA/SEG16
• Serial Clock (SCK) – RC3/SCK/SCL/SEG17
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS
) – RF7/AN5/SS/SEG25
Figure 18-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 18-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR reg
SSPM<3:0>
bit 0
Shift
Clock
SS
Control
Enable
Edge
Select
Clock Select
TMR2 Output
T
OSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TXx/RXx in SSPSR
TRIS bit
2
SMP:CKE
SDO
SSPBUF reg
SDI
SS
SCK