Datasheet

PIC18F87J72 FAMILY
DS39979A-page 176 Preliminary  2010 Microchip Technology Inc.
17.3.3.4 M3 (Hardware Contrast)
In M3, the LCD regulator is completely disabled. Like
M2, LCD bias levels are tied to AV
DD, and are generated
using an external divider. The difference is that the inter-
nal voltage reference is also disabled and the bottom of
the ladder is tied to ground (V
SS); see Figure 17-5. The
value of the resistors, and the difference between V
SS
and VDD, determine the contrast range; no software
adjustment is possible. This configuration is also used
where the LCD’s current requirements exceed the
capacity of the charge pump and software contrast
control is not needed.
Depending on the bias type required, resistors are
connected between some or all of the pins. A potentio-
meter can also be connected between LCDBIAS3 and
V
DD to allow for hardware controlled contrast
adjustment.
M3 is selected by clearing the CKSEL<1:0> and CPEN
bits.
FIGURE 17-5: RESISTOR LADDER CONNECTIONS FOR M3 CONFIGURATION
LCDBIAS3
Note 1: These values are provided for design guidance only; they should be optimized for the application by the
designer based on the actual LCD specifications.
2: Potentiometer for manual contrast adjustment is optional; it may be omitted entirely.
Bias Level at Pin
Bias Type
Static 1/2 Bias 1/3 Bias
LCDBIAS0 AV
SS AVSS AVSS
LCDBIAS1 AVSS 1/2 AVDD 1/3 AVDD
LCDBIAS2 AVDD 1/2 AVDD 2/3 AVDD
LCDBIAS3 AVDD AVDD AVDD
10 k
(1)
10 k
(1)
Static Bias 1/2 Bias 1/3 Bias
LCDBIAS2
LCDBIAS1
LCDBIAS0
AV
DD
10 k
(1)
10 k
(1)
10 k
(1)
VDD
(2)
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