Datasheet

PIC18F87J72 FAMILY
DS39979A-page 154 Preliminary  2010 Microchip Technology Inc.
15.3.2 ALARM INTERRUPT
At every alarm event, an interrupt is generated. Addi-
tionally, an alarm pulse output is provided that operates
at half the frequency of the alarm.
The alarm pulse output is completely synchronous with
the RTCC clock and can be used as a trigger clock to
other peripherals. This output is available on the RTCC
pin. The output pulse is a clock with a 50% duty cycle
and a frequency half that of the alarm event (see
Figure 15-6).
The RTCC pin can also output the seconds clock. The
user can select between the alarm pulse, generated by
the RTCC module, or the seconds clock output.
The RTSECSEL<1:0> (PADCFG1<2:1>) bits select
between these two outputs:
• Alarm Pulse – RTSECSEL<1:0> = 00
• Seconds Clock – RTSECSEL<1:0> = 01
FIGURE 15-6: TIMER PULSE GENERATION
15.4 Sleep Mode
The timer and alarm continue to operate while in Sleep
mode. The operation of the alarm is not affected by
Sleep as an alarm event can always wake-up the CPU.
The Idle mode does not affect the operation of the timer
or alarm.
15.5 Reset
15.5.1 DEVICE RESET
When a device Reset occurs, the ALCFGRPT register
is forced to its Reset state, causing the alarm to be
disabled (if enabled prior to the Reset). If the RTCC
was enabled, it will continue to operate when a basic
device Reset occurs.
15.5.2 POWER-ON RESET (POR)
The RTCCFG and ALRMRPT registers are reset only
on a POR. Once the device exits the POR state, the
clock registers should be reloaded with the desired
values.
The timer prescaler values can be reset only by writing
to the SECONDS register. No device Reset can affect
the prescalers.
RTCEN bit
ALRMEN bit
RTCC Alarm Event
RTCC Pin