Datasheet

PIC18F87J72 FAMILY
DS39979A-page 100 Preliminary  2010 Microchip Technology Inc.
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1
— ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 =High priority
0 = Low priority
bit 5 RC1IP: EUSART Receive Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 TX1IP: EUSART Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority