Datasheet

 2007-2012 Microchip Technology Inc. DS39778E-page 3
PIC18F87J11 FAMILY
Pin Diagrams (Continued)
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
4039
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
RE2/AD10/PMBE
(3)
/P2B
RE3/AD11/PMA13/P3C
(2)
/REFO
RE4/AD12/PMA12/P3B
(2)
RE5/AD13/PMA11/P1C
(2)
RE6/AD14/PMA10/P1B
(2)
RE7/AD15/PMA9/ECCP2
(1)
/P2A
(1)
RD0/AD0/PMD0
(3)
VDD VSS RD1/AD1/PMD1
(3)
RD2/AD2/PMD2
(3)
RD3/AD3/PMD3
(3)
RD4/AD4/PMD4
(3)
/SDO2
RD5/AD5/PMD5
(3)
/SDI2/SDA2
RD6/AD6/PMD6
(3)
/SCK2/SCL2
RD7/AD7/PMD7
(3)
/SS2
RE1/AD9/PMWR
(3)
/P2C
RE0/AD8/PMRD
(3)
/P2D
RG0/PMA8/ECCP3/P3A
RG1/PMA7/TX2/CK2
RG2/PMA6/RX2/DT2
RG3/PMCS1/CCP4/P3D
MCLR
RG4/PMCS2/CCP5/P1D
V
SS
VDDCORE/VCAP
RF7/PMD0
(3)
/SS1
RB0/INT0/FLT0
RB1/INT1/PMA4
RB2/INT2/PMA3
RB3/INT3/PMA2/ECCP2
(1)
/P2A
(1)
RB4/KBI0/PMA1
RB5/KBI1/PMA0
RB6/KBI2/PGC
V
SS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V
DD
RB7/KBI3/PGD
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
ENVREG
RF1/AN6/C2OUT
AV
DD
AVSS
RA3/AN3/VREF+
RA2/AN2/V
REF-
RA1/AN1 RA0/AN0
V
SS
VDD
RA4/PMD5
(3)
/T0CKI
RA5/PMD4
(3)
/AN4
RC1/T1OSI/ECCP2
(1)
/P2A
(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RC5/SDO1
RJ0/ALE RJ1/OE RH1/A17 RH0/A16
1
2
RH2/A18/PMD7
(3)
RH3/A19/PMD6
(3)
17
18
RH7/PMWR
(3)
/AN15/P1B
(2)
RH6/PMRD
(3)
/AN14/
RH5/PMBE
(3)
/AN13/P3B
(2)
/C2IND
RH4/PMD3
(3)
/AN12/P3C
(2)
/C2INC
RJ5/CE
RJ4/BA0
37
RJ7/UB
RJ6/LB
50
49
RJ2/WRL
RJ3/WRH
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 7378 77 76 757980
80-Pin TQFP
Legend: Shaded pins indicate pins that are tolerant up to +5.5V.
Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings.
2: P1B, P1C, P3B, and P3C pin placement depends on the ECCPMX Configuration bit setting.
3: PMP pin placement depends on the PMPMX Configuration bit setting.
RF5/PMD2
(3)
/AN10/
RF4/AN9/C2INA
RF3/AN8/C2INB
RF2/PMA5/AN7/C1OUT
RF6/PMD1
(3)
/AN11/C1INA
C1INB/CV REF
P1C
(2)
/C1INC
PIC18F8XJ11
PIC18F8XJ16