Datasheet

PIC18F87J11 FAMILY
DS39778E-page 238 2007-2012 Microchip Technology Inc.
FIGURE 20-1: MSSPx BLOCK DIAGRAM
(SPI MODE)
20.3.1 REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
MSSPx Control Register 1 (SSPxCON1)
MSSPx Status Register (SSPxSTAT)
Serial Receive/Transmit Buffer Register
(SSPxBUF)
MSSPx Shift Register (SSPxSR) – Not directly
accessible
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
( )
Read Write
Internal
Data Bus
SSPxSR Register
SSPM<3:0>
bit 0
Shift
Clock
SSx
Control Enable
Edge
Select
Clock Select
TMR2 Output
T
OSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TXx/RXx in SSPxSR
TRIS bit
2
SMP:CKE
SDOx
SDIx
SSx
SCKx
Note: Only port I/O names are used in this diagram
for the sake of brevity. Refer to the text for a
full list of multiplexed functions.
SSPxBUF Register
Note: Because the SSPxBUF register is
double-buffered, using read-modify-write
instructions, such as BCF, COMF, etc., will
not work.
Similarly, when debugging under an
in-circuit debugger, performing actions
that cause reads of SSPxBUF (mouse
hovering, watch, etc.) can consume data
that the application code was expecting to
receive.