Datasheet

PIC18F87J11 FAMILY
DS39778E-page 190  2007-2012 Microchip Technology Inc.
12.4.2 PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 12-28 shows an example of a
memory or peripheral that is partially multiplexed with
an external latch. If the peripheral has internal latches
as shown in Figure 12-29, then no extra circuitry is
required except for the peripheral itself.
FIGURE 12-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
FIGURE 12-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PMA<14:7>
D<7:0>
373
A<14:0>
D<7:0>
A<7:0>
PMRD
PMWR
OE
WR
CE
PIC18F
Address Bus
Data Bus
Control Lines
PMCS
PMALL
A<14:8>
PMD<7:0>
ALE
PMRD
PMWR
RD
WR
CS
PIC18F
Address Bus
Data Bus
Control Lines
PMCS
PMALL
AD<7:0>
Parallel Peripheral
PMD<7:0>