Datasheet

PIC18F87J11 FAMILY
DS39778E-page 12  2007-2012 Microchip Technology Inc.
TABLE 1-3: PIC18F6XJ1X PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
64-TQFP
MCLR
7 I ST Master Clear (Reset) input. This pin is an active-low Reset
to the device.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
39
I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input. Available only in
External Oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator input connection.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
Main clock input connection.
External clock source input. Always associated
with pin function, OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin. Available only in INTIO2 and
INTPLL2 Oscillator modes.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
40
O
O
I/O
—
—
TTL
Oscillator crystal or clock output. Available only in External
Oscillator modes (EC/ECPLL and HS/HSPLL).
Main oscillator feedback output connection.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
System cycle clock output (F
OSC/4).
In EC, ECPLL, INTIO1 and INTPLL1 Oscillator modes,
OSC2 pin outputs CLKO which has 1/4 the frequency
of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin. Available only in INTIO1 and
INTPLL1 Oscillator modes.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C = ST with I
2
C™ or SMB levels
Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared.