Datasheet

PIC18F87J11 FAMILY
DS39778E-page 10  2007-2012 Microchip Technology Inc.
FIGURE 1-1: PIC18F6XJ1X (64-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
Data Latch
Data Memory
(2.0, 3.9
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(96 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Tabl e 1- 3 for I/O port pin descriptions.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
EUSART1
Comparators
MSSP1
Timer2Timer1 Timer3Timer0
ECCP1
A/D
10-Bit
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ECCP2
ROM Latch
ECCP3
MSSP2CCP4 CCP5
PORTC
PORTD
PORTE
PORTF
PORTG
RA<7:0>
(1)
RC<7:0>
(1)
RD<7:0>
(1)
RE<7:0>
(1)
RF<7:2>
(1)
RG<4:0>
(1)
PORTB
RB<7:0>
(1)
Timer4
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
8 MHz
INTOSC
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
(2)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Kbytes)
PMP
Timing
Generation