Datasheet

PIC18F87J10 FAMILY
DS39663F-page 364 © 2009 Microchip Technology Inc.
27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
DC 25 MHz HS Oscillator mode
DC 40 MHz EC Oscillator mode
DC 10 MHz HSPLL, ECPLL Oscillator modes
Oscillator Frequency
(1)
4 25 MHz HS Oscillator mode
4 10 MHz HS/EC + PLL Oscillator mode
1T
OSC External CLKI Period
(1)
40 — ns HS Oscillator mode
25 — ns EC Oscillator mode
Oscillator Period
(1)
40 250 ns HS Oscillator mode
100 250 ns HS/EC + PLL Oscillator mode
2TCY Instruction Cycle Time
(1)
100 — ns TCY = 4/FOSC, Industrial
3T
OSL,
T
OSH
External Clock in (OSC1)
High or Low Time
10 — ns HS Oscillator mode
4TOSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4