Datasheet
© 2009 Microchip Technology Inc. DS39663F-page 257
PIC18F87J10 FAMILY
20.3.2 EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>), or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGHx:SPBRGx registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RCxIE.
5. If 9-bit reception is desired, set bit, RX9.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RCxIF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RCxIE, was set.
8. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREGx register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55
RCSTAx SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 55
RCREGx EUSARTx Receive Register 55
TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCONx
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 56
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
CREN bit
RC7/RX1/DT1
RC6/TX1/CK1 pin
Write to
bit SREN
SREN bit
RC1IF bit
(Interrupt)
Read
RCREG1
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘
0
’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0
’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2
(RG1/TX2/CK2 and RG2/RX2/DT2).
RC6/TX1/CK1 pin
pin
(SCKP = 0)
(SCKP = 1)